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| 7547 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0156-0121 Rev.1.21 Nov 15, 2006 DESCRIPTION The 7547 Group is the QzROM version of 7542 Group. The 7547 Group has the pin-compatibilty with the 7542 Group. As new functions, the power-on reset, the low voltage detection circuit, and the function set ROM are added. * * * * FEATURES * * * * * * * * * * * Basic machine-language instructions ...................................... 71 The minimum instruction execution time ............................. 0.25 s (at 8 MHz oscillation frequency, double-speed mode for the shortest instruction) Memory size ROM ................................ 8K, 16K bytes RAM ............................... 384, 512 bytes Programmable I/O ports ........................................................... 29 Interrupts ................................................. 18 sources, 16 vectors Timers ............................................................................. 8-bit 2 ...................................................................................... 16-bit 2 Output compare ............................................................ 4-channel Input capture ................................................................ 2-channel Serial interface ............ 8-bit 2 (UART or Clock-synchronized) A/D converter ............................................... 10-bit 8 channels Clock generating circuit ............................................. Built-in type (low-power dissipation by an on-chip oscillator) (connected to external ceramic resonator or quartz-crystal oscillator permitting RC oscillation) * * Watchdog timer ............................................................ 16-bit 1 Power-on reset circuit ............................................... Built-in type Low voltage detection circuit ..................................... Built-in type Power source voltage XIN oscillation frequency at ceramic oscillation, in double-speed mode At 8 MHz .................................................................... 4.5 to 5.5 V At 6.5 MHz ................................................................. 4.0 to 5.5 V At 2 MHz .................................................................... 2.4 to 5.5 V At 1 MHz .................................................................... 2.2 to 5.5 V XIN oscillation frequency at ceramic oscillation, in high-speed mode or middle-speed mode At 8 MHz .................................................................... 4.0 to 5.5 V At 4 MHz .................................................................... 2.4 to 5.5 V At 2 MHz .................................................................... 2.2 to 5.5 V XIN oscillation frequency at RC oscillation in high-speed mode or middle-speed mode At 4 MHz .................................................................... 4.0 to 5.5 V At 2 MHz .................................................................... 2.4 to 5.5 V At 1 MHz .................................................................... 2.2 to 5.5 V XIN oscillation frequency at on-chip oscillation ......... 1.8 to 5.5 V Power dissipation ................................................ 29.5 mW (Typ.) Operating temperature range ................................... -20 to 85 C Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 1 of 89 7547 Group PIN CONFIGURATION (TOP VIEW) P12/SCLK1 P13/SRDY1 P14/CNTR0 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 VREF RESET CNVSS Vcc XIN XOUT VSS 1 2 3 4 36 35 34 33 5 6 7 8 9 10 11 12 13 14 15 16 17 18 32 31 30 29 28 27 26 25 24 23 22 21 20 19 P11/TXD1 P10/RXD1/CAP0 P07(LED07)/SRDY2 P06(LED06)/SCLK2 P05(LED05)/TxD2 P04(LED04)/RxD2 P03(LED03)/TXOUT P02(LED02)/CMP1 P01(LED01)/CMP0 P00(LED00)/CAP0 P37(LED17)/INT0 P36(LED16)/INT1 P35(LED15) P34(LED14) P33(LED13)/INT1 P32(LED12)/CMP3 P31(LED11)/CMP2 P30(LED10)/CAP1 Package type: PRSP0036GA-B (36P2R-D) Fig. 1 Pin configuration (Package type: PRSP0036GA-B) M37547Gx-XXXFP M37547GxFP Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 2 of 89 7547 Group Table 1 Performance overview Function 71 0.25 s (Minimum instruction, oscillation frequency 8 MHz: double-speed mode) Oscillation frequency 8 MHz (max.) Memory sizes ROM 8 K to 16 K bytes RAM 384 to 512 bytes I/O port P0, P1, P2, P3 *8-bit 3, 5-bit 1 Interrupts 18 sources, 16 vectors Timer *8-bit 2, 16-bit 2 Output compare 4 channel Input capture 2 channel Serial interface 8-bit 2 (UART or clock synchronous) A/D converter 10-bit 8 channel Watchdog timer 16-bit 1 Clock generating circuit Built-in (external ceramic resonator or quartz-crystal oscillator, RC oscillation available) (Low consumption current by on-chip oscillator available) Power source Double-speed mode At 8MHz oscillation 4.5 to 5.5 V voltage At 6.5MHz oscillation 4.0 to 5.5 V (at ceramic At 2MHz oscillation 2.4 to 5.5 V resonance) At 1MHz oscillation 2.2 to 5.5 V High-speed mode At 8MHz oscillation 4.0 to 5.5 V Middle-speed mode At 4MHz oscillation 2.4 to 5.5 V At 2MHz oscillation 2.2 to 5.5 V Power source High-speed mode At 4MHz oscillation 4.0 to 5.5 V voltage Middle-speed mode At 2MHz oscillation 2.4 to 5.5 V (at RC oscillation) At 1MHz oscillation 2.2 to 5.5 V Power source voltage (at on-chip oscillation) 1.8 to 5.5 V Power dissipation 29.5 mW (Typ.) Operating temperature range -20 to 85 C Device structure CMOS sillicon gate Package 36-pin plastic molded SSOP Number of basic instructions Instruction execution time Parameter Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 3 of 89 FUNCTIONAL BLOCK DIAGRAM (Package type: PRSP0036GA-B) [7547 Group] Reset input VSS 18 15 13 14 7547 Group Clock input Clock output VCC CNVSS RESET X IN X OUT 12 26 25 24 23 22 21 20 19 11 10 9 8 7 6 5 4 3 2 1 36 35 34 33 32 31 30 29 28 27 VREF I/O port P3 I/O port P2 I/O port P1 I/O port P0 Key-on wakeup Rev.1.21 Nov 15, 2006 REJ03B0156-0121 CPU 16 17 Clock generating circuit Fig. 2 Functional block diagram (Package type: PRSP0036GA-B) page 4 of 89 RAM X Prescaler X (8) CNTR0 ROM Y S PC H PS PCL A Prescaler 1 (8) Timer 1 (8) Timer X (8) Power-on reset circuit Reset Timer A (16) Timer B (16) Low voltage detection circuit Reset Watchdog timer Reset 0 A/D converter (10) Output Compare SI/O2(8) Input Capture SI/O1(8) INT0 INT1 P3(8) P2(8) P1(5) P0(8) 7547 Group PIN DESCRIPTION Table 2 Pin description Name Pin Power source Vcc, Vss Analog referVREF ence voltage CNVss CNVss Reset input RESET Clock input XIN Function Apply voltage of 1.8 to 5.5 V to Vcc, and 0 V to Vss. *Reference voltage input pin for A/D converter. Function expect a port function XOUT Clock output P00(LED00)/CAP0 I/O port P0 P01(LED01)/CMP0 P02(LED02)/CMP1 P03(LED03)/TXOUT P04(LED04)/RxD2 P05(LED05)/TxD2 P06(LED06)/SCLK2 P07(LED07)/SRDY2 I/O port P1 P10/RxD1/CAP0 P11/TxD1 P12/SCLK1 P13/SRDY1 P14/CNTR0 P20/AN0-P27/AN7 *Chip operating mode control pin, which is always connected to Vss. *Reset input pin for active "L" *Input and output pins for main clock generating circuit. *Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins. *For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor. *If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. *When the on-chip oscillator is selected as the main clock, connect XIN pin to VCC and leave XOUT open. *8-bit I/O port. * Capture function pin * Key-input *I/O direction register allows each pin to be individually pro- * Compare function pin (key-on wake up grammed as either input or output. *CMOS compatible input level * Timer X function pin interrupt *CMOS 3-state output structure * Serial I/O2 function pin input) pin *Whether a built-in pull-up resistor is to be used or not can be determined by program. * High drive capacity for LED drive port can be selected by program. *5-bit I/O port *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level *CMOS 3-state output structure *CMOS/TTL level can be switched for P10, P12 and P13 *8-bit I/O port having almost the same function as P0 *CMOS compatible input level *CMOS 3-state output structure *8-bit I/O port *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level (CMOS/TTL level can be switched for P36 and P37). *CMOS 3-state output structure *Whether a built-in pull-up resistor is to be used or not can be determined by program. * High drive capacity for LED drive port can be selected by program. * Serial I/O1 function pin * Capture function pin * Serial I/O1 function pin I/O port P2 * Timer X function pin * Input pins for A/D converter P30(LED10)/CAP1 P31(LED11)/CMP2 P32(LED12)/CMP3 P33(LED13)/INT1 P34(LED14) P35(LED15) P36(LED16)/INT1 P37(LED17)/INT0 I/O port P3 * Capture function pin * Compare function pin * Interrupt input pin * Interrupt input pin Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 5 of 89 7547 Group GROUP EXPANSION Renesas plans to expand the 7547 Group as follow: Memory type Support for QzROM Memory size ROM size ............................................................. 8 K to 16 K bytes RAM size .............................................................. 384 to 512 bytes Package PRSP0036GA-B .......... 0.8 mm-pitch 36-pin plastic molded SSOP ROM size (bytes) 16K M37547G4 8K M37547G2 0 384 512 RAM size (bytes) **: Under development Note: Products under development...the development schedule and specification may be revised without notice. Fig. 3 Memory expansion plan Currently supported products are listed below. Table 3 List of supported products Product M37547G2-XXXFP M37547G2FP M37547G4-XXXFP M37547G4FP ROM size (bytes) ROM size for User ( ) 8192 (8062) 16384 (16254) (Note) RAM size (bytes) 384 Package PRSP0036GA-B PRSP0036GA-B (Note) 512 PRSP0036GA-B PRSP0036GA-B Remarks Shipped after writing Shipped in blank Shipped after writing Shipped in blank Note : ROM size includes the function set ROM. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 6 of 89 7547 Group FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The MCU uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine-language instructions or the SERIES 740 Stack pointer (S) The stack pointer is an 8-bit register used during subroutine calls and interrupts. The stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Selection Bit. If the Stack Page Selection Bit is "0", then the RAM in the zero page is used as the stack area. If the Stack Page Selection Bit is "1", then RAM in page 1 is used as the stack area. The Stack Page Selection Bit is located in the SFR area in the zero page. Note that the initial value of the Stack Page Selection Bit varies with each microcomputer type. Also some microcomputer types have no Stack Page Selection Bit and the upper eight bits of the stack address are fixed. The operations of pushing register contents onto the stack and popping them from the stack are shown in Fig. 5. Accumulator (A) The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. Index register X (X), Index register Y (Y) Both index register X and index register Y are 8-bit registers. In the index addressing modes, the value of the OPERAND is added to the contents of register X or register Y and specifies the real address. When the T flag in the processor status register is set to "1", the value contained in index register X becomes the address for the second OPERAND. Program counter (PC) The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. b7 b0 A b7 b0 Accumulator Index Register X b0 X b7 Y b7 b0 Index Register Y Stack Pointer b0 S b15 b7 PCH b7 PCL b0 Program Counter N V T B D I Z C Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag Fig. 4 740 Family CPU register structure Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 7 of 89 7547 Group On-going Routine Interrupt request (Note) Execute JSR M (S) Store Return Address on Stack (S) M (S) (S) (PCH) (S - 1) (PCL) (S - 1) M (S) (S) M (S) (S) M (S) (S) (PCH) (S - 1) (PCL) (S - 1) (PS) (S - 1) Store Contents of Processor Status Register on Stack Store Return Address on Stack Subroutine Execute RTS Restore Return Address (S) (PCL) (S) (PCH) (S + 1) M (S) (S + 1) M (S) Interrupt Service Routine Execute RTI (S) (PS) (S) (PCL) (S) (PCH) (S + 1) M (S) (S + 1) M (S) (S + 1) M (S) I Flag "0" to "1" Fetch the Jump Vector Restore Contents of Processor Status Register Restore Return Address Note : The condition to enable the interrupt Interrupt enable bit is "1" Interrupt disable flag is "0" Fig. 5 Register push and pop at interrupt generation and subroutine call Table 4 Push and pop instructions of accumulator or processor status register Accumulator Processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 8 of 89 7547 Group Processor status register (PS) The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. After reset, the Interrupt disable (I) flag is set to "1", but all other flags are undefined. Since the Index X mode (T) and Decimal mode (D) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. (2) Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". (3) Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". When an interrupt occurs, this flag is automatically set to "1" to prevent other interrupts from interfering until the current interrupt is serviced. (4) Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. (5) Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". The saved processor status is the only place where the break flag is ever set. (6) Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations, i.e. between memory and memory, memory and I/O, and I/O and I/O. In this case, the result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1. The address of memory location 1 is specified by index register X, and the address of memory location 2 is specified by normal addressing modes. (7) Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. (8) Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag SEC CLC Z flag - - I flag SEI CLI D flag SED CLD B flag - - T flag SET CLT V flag - CLV N flag - - Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 9 of 89 7547 Group Memory Special function register (SFR) area The SFR area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for a stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. Interrupt vector area The interrupt vector area contains reset and interrupt vectors. Zero page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. ROM Code Protect Address (address FFDB16) Address FFDB16, which is the reserved ROM area of QzROM, is the ROM code protect address. "0016" is written into this address when selecting the protect bit write by using a serial programmer or selecting protect enabled for writing shipment by Renesas Technology corp.. When "0016" is set to the ROM code protect address, the protect function is enabled, so that reading or writing from/to QzROM is disabled by a serial programmer. As for the QzROM product in blank, the ROM code is protected by selecting the protect bit write at ROM writing with a serial programmer. As for the QzROM product shipped after writing, "0016" (protect enabled) or "FF16" (protect disabled) is written into the ROM code protect address when Renesas Technology corp. performs writing. The writing of "0016" or "FF16" can be selected as the ROM option setup (referred to as "Mask option setup" in MM) when ordering. s Notes Because the contents of RAM are indefinite at reset, set initial values before using. 000016 SFR area 004016 RAM area RAM capacity (bytes) 384 512 address XXXX16 01BF16 023F16 Zero page RAM 010016 XXXX16 Function set ROM consists of the followings: - Function set ROM data to set peripheral functions to be active immediately after system is released from reset, - ROM code protect to disable the reading of the built-in PROM area by serial programmer, - Renesas shipment test area where random data are written in when shipment test is performed by Renesas. Reserved area 044016 Not used Address FFD416 Renesas shipment test area FFD516 Renesas shipment test area FFD616 Renesas shipment test area FFD716 Renesas shipment test area FFD816 Function set ROM data 0 FFDA16 FFDB16 FFD916 Function set ROM data 1 Function set ROM data 2 ROM code protect YYYY16 Reserved ROM area (128 bytes) ZZZZ16 ROM FF0016 FFD4 16 Function set ROM function area Interrupt vector area Reserved ROM area Special page ROM area ROM capacity (bytes) 8192 16384 address YYYY16 E00016 C00016 address ZZZZ16 E08016 C08016 FFDC16 FFFE16 FFFF16 Fig. 6 Memory map diagram Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 10 of 89 7547 Group [CPU mode register] CPUM The CPU mode register contains the stack page selection bit, etc.. This register is allocated at address 003B16. Some function of the CPU mode register can be controlled by the function set ROM data 2. b7 b0 CPU mode register (Note 1) (CPUM: address 003B16, initial value: 8016) Processor mode bits b1 b0 0 0 Single-chip mode 0 1 Not available 1 0 Not available 1 1 Not available Stack page selection bit 0 : 0 page 1 : 1 page On-chip oscillator oscillation control bit (Note 3) 0 : On-chip oscillator oscillation enabled 1 : On-chip oscillator oscillation stop XIN oscillation control bit 0 : Ceramic or RC oscillation enabled 1 : Ceramic or RC oscillation stop Switching method of CPU mode register Switch the CPU mode register (CPUM) at the head of program after releasing Reset in the following method. Control by Function set ROM data 2 (FSROM2: address FFDA16) (Note 2) This cannot be controlled by FSROM2. This cannot be controlled by FSROM2. This bit function can be set by setting bit 4 of FSROM2. (Note 3) Bit 4 of FSROM2 = 0: Bit 3 of CPUM is fixed to "0". Bit 4 of FSROM2 = 1: Bit 3 of CPUM is "0" or "1". This cannot be controlled by FSROM2. This bit function can be set by setting bit 5 of FSROM2. (Note 4) Oscillation mode selection bit (Note 1, Note 4) Bit 5 of FSROM2 = 0: Bit 5 of CPUM is fixed to "0". 0 : Ceramic oscillation Bit 5 of FSROM2 = 1: Bit 5 of CPUM is "0" or "1". 1 : RC oscillation Clock division ratio selection bits This cannot be controlled by FSROM2. b7 b6 0 0 : f() = f(XIN)/2 (High-speed mode) 0 1 : f() = f(XIN)/8 (Middle-speed mode) 1 0 : applied from on-chip oscillator 1 1 : f() = f(XIN)/1 (Double-speed mode)(Note 5) Note 1: When the setting by the function set ROM data 2 (FSROM2) is performed, the initial value of CPUM is changed after releasing reset since bit 5 of CPUM is fixed. 2: The setting values of FSROM2 become valid by setting "0" to bit 0 of function set ROM data 0 (FSROM0). The setting values of FSROM2 are invalid by setting "1" to this bit. (In order that FSROM2 is invalid, write to CPUM after releasing reset.) 3: When bit 4 of FSROM2 is set to "0", the operation of on-chip oscillator cannot be stopped. Since the on-chip oscillator is not stopped also in the stop mode, the dissipation current in the stop mode is increased. 4: The setting value of bit 5 of CPUM can be fixed after releasing reset by setting value of bit 5 of FSROM2. Also, when the setting of FSROM2 is invalid, this bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to this bit. This bit is initialized by reset, and then, rewriting it is enabled. 5: This setting can be used only at ceramic oscillation. Do not use this at RC oscillation. Fig. 7 Structure of CPU mode register After releasing reset Start with an on-chip oscillator Switch the oscillation mode selection bit (bit 5 of CPUM) An initial value is set as a ceramic oscillation mode. When it is switched to an RC oscillation, its oscillation starts. When using a ceramic oscillation, wait until establlishment of oscillation from oscillation starts. When using an RC oscillation, wait time is not required basically (time to execute the instruction to switch from an on-chip oscillator meets the requirement). Select 1/1, 1/2, 1/8 or on-chip oscillator. Wait by on-chip oscillator operation until establishment of oscillator clock Switch the clock division ratio selection bits (bits 6 and 7 of CPUM) Main routine Note: After system is released from reset, an on-chip oscillator turns active automatically and system operation is started. Fig. 8 Switching method of CPU mode register Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 11 of 89 7547 Group 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Reserved Reserved Interrupt source set register (INTSET) Interrupt source discrimination register (INTDIS) Capture register 0 (low-order) (CAP0L) Capture register 0 (high-order) (CAP0H) Capture register 1 (low-order) (CAP1L) Capture register 1 (high-order) (CAP1H) Compare register (low-order) (CMPL) Compare register (high-order) (CMPH) Capture/compare register R/W pointer (CCRP) Capture software trigger register (CSTR) Compare register re-load register (CMPR) Port P0P3 drive capacity control register (DCCR) Pull-up control register (PULL) Port P1P3 control register (P1P3C) Transmit 1 /Receive 1 buffer register (TB1/RB1) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART1 control register (UART1CON) Baud rate generator 1 (BRG1) Timer A, B mode register (TABM) Capture/compare port register (CCPR) Timer source selection register (TMSR) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Capture mode register (CAPM) Compare output mode register (CMOM) Capture/compare status register (CCSR) Compare interrupt source set register (CISR) Timer A (low-order) (TAL) Timer A (high-order) (TAH) Timer B (low-order) (TBL) Timer B (high-order) (TBH) Prescaler 1 (PRE1) Timer 1 (T1) Timer count source set register (TCSS) Timer X mode register (TXM) Prescaler X (PREX) Timer X (TX) Transmit 2 / Receive 2 buffer register (TB2/RB2) Serial I/O2 status register (SIO2STS) Serial I/O2 control register (SIO2CON) UART2 control register (UART2CON) Baud rate generator 2 (BRG2) Reserved A/D control register (ADCON) A/D conversion register (low-order) (ADL) A/D conversion register (high-order) (ADH) On-chip oscillation division ratio selection register (RODR) MISRG Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Notes 1: Do not access to the SFR area including nothing. Fig. 9 Memory map of special function register (SFR) Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 12 of 89 7547 Group I/O Ports [Direction registers] PiD The I/O ports have direction registers which determine the input/ output direction of each pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input or output. When "1" is set to the bit corresponding to a pin, this pin becomes an output port. When "0" is set to the bit, the pin becomes an input port. When data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. Pins set to input are floating, and permit reading pin values. If a pin set to input is written to, only the port latch is written to and the pin remains floating. [Port P0P3 drive capacity control register] DCCR By setting the Port P0P3 drive capacity control register (address 001516), the drive capacity of the N-channel output transistor for the port P0 and port P3 can be selected. [Pull-up control register] PULL By setting the pull-up control register (address 001616), ports P0 and P3 can exert pull-up control by program. However, pins set to output are disconnected from this control and cannot exert pull-up control. [Port P1P3 control register] P1P3C By setting the port P1P3 control register (address 001716), a CMOS input level or a TTL input level can be selected for ports P10, P12, P13, P36, and P37 by program. b7 b0 Port P0P3 drive capacity control register (DCCR: address 001516, initial value: 0016) Port P00 drive capacity bit Ports P01, P02 drive capacity bit Ports P03-P07 drive capacity bit Port P30 drive capacity bit Ports P31, P32 drive capacity bit Port P33 drive capacity bit Ports P34, P35 drive capacity bit Ports P36, P37 drive capacity bit 0 : Low 1 : High Note: Number of LED drive port (drive capacity is HIGH) is 8-port. Fig. 10 Structure of port P0P3 drive capacity control register b7 b0 Pull-up control register (PULL: address 001616, initial value: 0016) P00 pull-up control bit P01, P02 pull-up control bit P03-P07 pull-up control bit P30 pull-up control bit P31, P32 pull-up control bit P33 pull-up control bit P34, P35 pull-up control bit P36, P37 pull-up control bit 0 : Pull-up Off 1 : Pull-up On Note : Pins set to output ports are disconnected from pull-up control. Fig. 11 Structure of pull-up control register b7 b0 Port P1P3 control register (P1P3C: address 001716, initial value: 0016) P37/INT0 input level selection bit 0 : CMOS level 1 : TTL level P36/INT1 input level selection bit 0 : CMOS level 1 : TTL level P10,P12,P13 input level selection bit 0 : CMOS level 1 : TTL level Not used Fig. 12 Structure of port P1P3 control register Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 13 of 89 7547 Group Table 6 I/O port function table Pin P00(LED00)/CAP0 Name I/O format Non-port function SFRs related each pin Diagram No. (1) I/O port P0 *CMOS compatible * Capture function input input level (Note 1) * Key input interrupt *CMOS 3-state output P01(LED01)/CMP0 P02(LED02)/CMP1 P03(LED03)/TXOUT P04(LED04)/RxD2 P05(LED05)/TxD2 P06(LED06)/SCLK2 P07(LED07)/SRDY2 P10/RxD1/CAP0 I/O port P1 P11/TxD1 P12/SCLK1 P13/SRDY1 P14/CNTR0 P20/AN0-P27/AN7 P30(LED10)/CAP1 I/O port P2 I/O port P3 Capture/Compare port register Interrupt edge selection register Pull-up control register Port P0P3 drive capacity control register * Compare function output Capture/Compare port register * Key input interrupt Pull-up control register Port P0P3 drive capacity control register * Timer X function output Timer X mode register * Key input interrupt Pull-up control register Port P0P3 drive capacity control register * Serial I/O2 function input/output Serial I/O2 control register * Key input interrupt Interrupt edge selection register Pull-up control register Port P0P3 drive capacity control register Serial I/O2 control register Pull-up control register Port P0P3 drive capacity control register Serial I/O2 control register Interrupt edge selection register Pull-up control register Port P0P3 drive capacity control register Serial I/O2 control register Pull-up control register Port P0P3 drive capacity control register * Serial I/O1 function input Serial I/O1 control register * Capture function input Capture/Compare port register Port P1P3 control register * Serial I/O1 function input/output Serial I/O1 control register Serial I/O1 control register Port P1P3 control register Serial I/O1 control register Port P1P3 control register * Timer X function input/output Timer X mode register * External interrupt input * A/D conversion input A/D control register * Capture function input Capture/Compare port register Pull-up control register Port P0P3 drive capacity control register Capture/Compare port register Pull-up control register Port P0P3 drive capacity control register Interrupt edge selection register Pull-up control register Port P0P3 drive capacity control register Pull-up control register Port P0P3 drive capacity control register Interrupt edge selection register Pull-up control register Port P0P3 drive capacity control register Port P1P3 control register (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) P31(LED11)/CMP2 P32(LED12)/CMP3 P33(LED13)/INT1 * Compare function output (15) * External interrupt input (16) P34(LED14) P35(LED15) P36(LED16)/INT1 P37(LED17)/INT0 (17) (18) (19) * External interrupt input Notes 1: Ports P10, P12, P13, P36, and P37 are CMOS/TTL level. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 14 of 89 7547 Group (1) Port P00 Pull-up control Direction register (2) Ports P01, P02 Compare output control Direction register Pull-up control Data bus Port latch Drive capacity control Capture 0 input Capture 0 input control To key input interrupt generating circuit Data bus Port latch Drive capacity control Compare output P00 key-on wakeup selection bit To key input interrupt generating circuit (3) Port P03 P03/TXOUT output valid Direction register Pull-up control (4) Port P04 Serial I/O2 enable bit Receive enable bit Direction register Data bus Port latch Pull-up control Data bus Port latch Drive capacity control Drive capacity control Timer output To key input interrupt generating circuit Serial I/O2 input To key input interrupt generating circuit P04 key-on wakeup selection bit (5) Port P05 Serial I/O2 enable bit Transmit enable bit Direction register Data bus Port latch Drive capacity control Pull-up control (6) Port P06 Serial I/O2 synchronous clock selection bit Serial I/O2 enable bit Serial I/O2 mode selection bit Serial I/O2 enable bit Direction register Data bus Port latch Drive capacity control Pull-up control Serial I/O2 output To key input interrupt generating circuit Serial I/O2 clock output Serial I/O2 clock input To key input interrupt generating circuit P06 key-on wakeup selection bit (7) Port P07 Serial I/O2 mode selection bit Serial I/O2 enable bit SRDY2 output enable bit Direction register Data bus Port latch Drive capacity control Pull-up control Serial I/O2 ready output To key input interrupt generating circuit Fig. 13 Block diagram of ports (1) Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 15 of 89 7547 Group (8) Port P10 Serial I/O1 enable bit Receive enable bit Direction register Data bus Port latch P10, P12, P13 input level selection bit (9) Port P11 P11/TxD1 P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Direction register Data bus Port latch Serial I/O1 input Capture 0 input control Capture 0 input * Serial I/O1 output (10) Port P12 Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register (11) Port P13 Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register Data bus Data bus Port latch Port latch P10, P12, P13 input level selection bit P10, P12, P13 input level selection bit Serial I/O1 clock output Serial I/O1 ready output * * (13) Ports P20-P27 Direction register Serial I/O1 clock input (12) Port P14 Pulse output mode Direction register Data bus Port latch Data bus Port latch Timer output CNTR0 interrupt input A/D converter input Analog input pin selection bit * P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register. When the TTL level is selected, there is no hysteresis characteristics. Fig. 14 Block diagram of ports (2) Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 16 of 89 7547 Group (14) Port P30 Pull-up control Direction register (15) Ports P31, P32 Compare output control Direction register Pull-up control Data bus Port latch Drive capacity control Capture 1 input Capture 1 input control Data bus Port latch Drive capacity control Compare output (16) Port P33 Pull-up control Direction register (17) Ports P34, P35 Pull-up control Direction register Data bus Port latch Drive capacity control Data bus Port latch Drive capacity control INT1 input control INT1 input (18) Port P36 Pull-up control Direction register (19) Port P37 Pull-up control Direction register Data bus Port latch Drive capacity control Data bus Port latch Drive capacity control P3 input level selection bit P3 input level selection bit INT1 input control INT1 input * INT0 input * * P10, P12, P13, P36, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register. When the TTL level is selected, there is no hysteresis characteristics. Fig. 15 Block diagram of ports (3) Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 17 of 89 7547 Group Termination of unused pins * Termination of common pins I/O ports: Select an input port or an output port and follow each processing method. Output ports: Open. Input ports: If the input level become unstable, through current flow to an input circuit, and the power supply current may increase. Especially, when expecting low consumption current (at STP or WIT instruction execution etc.), pull-up or pull-down input ports to prevent through current (built-in resistor can be used). We recommend processing unused pins through a resistor which can secure IOH(avg) or IOL(avg). Because, when an I/O port or a pin which have an output function is selected as an input port, it may operate as an output port by incorrect operation etc. Table 7 Termination of unused pins Termination 1 Termination 2 (recommend) I/O port When selecting CAP function, perP00/CAP0 form termination of input port. When selecting CMP0 function, P01/CMP0 perform termination of output port. When selecting CMP1 function, P02/CMP1 perform termination of output port. When selecting TXOUT function, P03/TXOUT perform termination of output port. When selecting RxD2 function, P04/RxD2 perform termination of input port. When selecting TxD2 function, P05/TxD2 perform termination of output port. P06/SCLK2 When selecting external clock input, perform termination of output port. P07/SRDY2 When selecting SRDY2 function, perform termination of output port. P10/RxD1/CAP0 When selecting RxD1 function, perform termination of input port. P11/TxD1 When selecting TxD1 function, perform termination of output port. P12/SCLK1 When selecting external clock input, perform termination of input port. P13/SRDY1 When selecting SRDY1 function, perform termination of output port. P14/CNTR0 When selecting CNTR input function, perform termination of input port. P20/AN0-P27/AN7 When selecting AN function, perform termination of input port. P30/CAP1 When selecting CAP function, perform termination of input port. P31/CMP2 When selecting CMP2 function, perform termination of output port. P32/CMP3 When selecting CMP3 function, perform termination of output port. P33/INT1 When selecting INT function, perform termination of input port. P34 Pin P35 P36/INT1 P37/INT0 VREF When selecting INT function, perform termination of input port. When selecting INT function, perform termination of input port. Connect to Vss. Termination 3 When selecting internal clock output, perform termination of output port. When selecting CAP function, perform termination of input port. When selecting internal clock output, perform termination of output port. When selecting CNTR output function, perform termination of output port. Termination 4 When selecting key-on wakeup function, perform termination of input port. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 18 of 89 7547 Group Interrupts Interrupts occur by 18 different sources : 6 external sources, 11 internal sources and 1 software source. Interrupt control All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. When the interrupt enable bit and the interrupt request bit are set to "1" and the interrupt disable flag is set to "0", an interrupt is accepted. The interrupt request bit can be cleared by program but not be set. The interrupt enable bit can be set and cleared by program. The reset and BRK instruction interrupt can never be disabled with any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set. When several interrupts occur at the same time, the interrupts are received according to priority. Interrupt operation Upon acceptance of an interrupt the following operations are automatically performed: 1. The processing being executed is stopped. 2. The contents of the program counter and processor status register are automatically pushed onto the stack. 3. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. Concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter. [Interrupt source set register] INTSET When two interrupt sources are assigned to the same interrupt vector, the valid/invalid of each interrupt is set by this register. When both two interrupt sources are set to be valid, which interrupt request occurs is confirmed by the next interrupt source discrimination register. [Interrupt source discrimination register] INTDIS When two interrupt sources are assigned to the same interrupt vector, which interrupt source occurs is confirmed by this register. If an interrupt request of a key-on wakeup, UART1 bus collision detection, A/D conversion or timer 1 occurs, an interrupt discrimination bit is set to "1" regardless of valid/invalid state by the interrupt source set register. However, when the interrupt valid bit of an interrupt source set register is "0" (invalid), the interrupt request bit of an interrupt control register is not set to "1." Moreover, since an interrupt discrimination bit is not automatically cleared to "0" by interrupt, please clear it by program. An interrupt discrimination bit can be cleared to "0" by program but not be set to "1." [Interrupt edge selection register] INTEDGE The valid edge of external interrupt INT0 and INT1 can be selected by the interrupt edge selection bit, respectively. For the external interrupt INT1, the external input pin P33/INT1 or P36/INT1 can be selected by the INT1 input port selection bit. By the key-on wakeup selection bit, enable/disable of a key-on wakeup of P00, P04, and P06 pins can be selected, respectively. s Notes on use (1) When setting the followings, the interrupt request bit may be set to "1". *When switching external interrupt active edge Related register: Interrupt edge selection register (address 003A16) Timer X mode register (address 002B16) Capture mode register (address 002016) When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. Set the corresponding interrupt enable bit to "0" (disabled). Set the interrupt edge select bit (active edge switch bit, trigger mode bit). Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. Set the corresponding interrupt enable bit to "1" (enabled). (2) Use a LDM instruction to clear an interrupt discrimination bit. LDM #$0n, $0B Set the following values to "n" "0": an interrupt discrimination bit to clear "1": other interrupt discrimination bits Ex.) When a key-on wakeup interrupt discrimination bit is cleared; LDM #00001110B and $0B. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 19 of 89 7547 Group Table 8 Interrupt vector address and priority Interrupt source Priority Reset (Note 2) Serial I/O1 receive Serial I/O1 transmit Serial I/O2 receive Serial I/O2 transmit INT0 INT1 Key-on wake-up/ UART1 bus collision detection (Note 3) CNTR0 Capture 0 Capture 1 Compare Timer X Timer A Timer B A/D conversion/ Timer 1 (Note 4) BRK instruction 1 2 3 4 5 6 7 8 Vector addresses (Note 1) High-order FFFD16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 Low-order FFFC16 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 Interrupt request generating conditions At reset input At completion of serial I/O1 data receive At completion of serial I/O1 transmit shift or when transmit buffer is empty At completion of serial I/O2 data receive At completion of serial I/O2 transmit shift or when transmit buffer is empty At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At falling of conjunction of input logical level for port P0 (at input) At detection of UART1 bus collision detection At detection of either rising or falling edge of CNTR0 input Remarks Non-maskable Valid only when serial I/O1 is selected Valid only when serial I/O1 is selected Valid only when serial I/O2 is selected Valid only when serial I/O2 is selected 9 10 11 12 13 14 15 16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid at falling, when key-on wakeup interrupt is enabled) When UART1 bus collision detection interrupt is enabled. External interrupt (active edge selectable) At detection of either rising or falling edge External interrupt (active edge selectable) of Capture 0 input At detection of either rising or falling edge External interrupt (active edge selectable) of Capture 1 input Compare interrupt source is selected. At compare matched At timer X underflow At timer A underflow At timer B underflow At completion of A/D conversion At timer 1 underflow At BRK instruction execution 17 FFDD16 FFDC16 When A/D conversion interrupt is enabled. STP release timer underflow (When Timer 1 interrupt is enabled) Non-maskable software interrupt Note 1: Vector addressed contain internal jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. 3: Key-on wakeup interrupt and UART1 bus collision detection interrupt can be enabled by setting of interrupt source set register. The occurrence of these interrupts are discriminated by interrupt source discrimination register. 4: A/D conversion interrupt and Timer 1 interrupt can be enabled by setting of interrupt source set register. The occurrence of these interrupts are discriminated by interrupt source discrimination register. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 20 of 89 7547 Group Key-on wakeup interrupt discrimination bit Key-on wakeup interrupt request Key-on wakeup interrupt valid bit UART1 bus collision detection interrupt discrimination bit Key-on wakeup/ UART1 bus collision detection interrupt request bit UART1 bus collision detection interrupt request UART1 bus collision detection interrupt valid bit A/D conversion interrupt discrimination bit A/D conversion interrupt request A/D conversion interrupt valid bit Timer 1 interrupt discrimination bit A/D conversion/ Timer 1 interrupt request bit Timer 1 interrupt request Timer 1 interrupt valid bit Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request Note: For key-on wakeup, UART1 bus collision detection, A/D conversion and Timer 1 interrupt, even if interrupt valid bit (000A16) is set "0: Invalid", interrupt discrimination bit (000B16) is set to "1: interrupt occurs" when corresponding interrupt request occurs. But corresponding interrupt request bit (003C16, 003D16) is not set to "1". Fig. 16 Interrupt control Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 21 of 89 7547 Group b7 b0 b7 Interrupt source set register (INTSET: address 000A16, initial value: 0016) Key-on wakeup interrupt valid bit UART1 bus collision detection interrupt valid bit A/D conversion interrupt valid bit Timer 1 interrupt valid bit Not used (returns "0" when read) 0: Interrupt invalid 1: Interrupt valid b0 Interrupt request register 1 (IREQ1 : address 003C16, initial value : 0016) Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Serial I/O2 receive interrupt request bit Serial I/O2 transmit interrupt request bit INT0 interrupt request bit INT1 interrupt request bit Key-on wake up/UART1 bus collision detection interrupt request bit CNTR0 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt source discrimination register (INTDIS: address 000B16, initial value: 0016) Key-on wakeup interrupt discrimination bit UART1 bus collision detection interrupt discrimination bit A/D conversion interrupt discrimination bit Timer 1 interrupt discrimination bit Not used (returns "0" when read) 0: Interrupt does not occur 1: Interrupt occurs b7 b0 Interrupt request register 2 (IREQ2 : address 003D16, initial value : 0016) Capture 0 interrupt request bit Capture 1 interrupt request bit Compare interrupt request bit Timer X interrupt request bit Timer A interrupt request bit Timer B interrupt request bit A/D conversion/Timer 1 interrupt request bit Not used (returns "0" when read) (Do not write "1" to this bit) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt edge selection register (INTEDGE : address 003A16, initial value: 0016) INT0 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active INT1 interrupt edge selection bit 0 : Falling edge active 1 : Rising edge active INT1 input port selection bit 0 : P36 1 : P33 Not used (returns "0" when read) P00 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled P04 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled P06 key-on wakeup enable bit 0 : Key-on wakeup enabled 1 : Key-on wakeup disabled b7 b0 Interrupt control register 1 (ICON1 : address 003E16, initial value : 0016) Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Serial I/O2 receive interrupt enable bit Serial I/O2 transmit interrupt enable bit INT0 interrupt enable bit INT1 interrupt enable bit Key-on wake up/UART1 bus collision detection interrupt enable bit CNTR0 interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled b0 Interrupt control register 2 (ICON2 : address 003F16, initial value : 0016) Capture 0 interrupt enable bit Capture 1 interrupt enable bit Compare interrupt enable bit Timer X interrupt enable bit Timer A interrupt enable bit Timer B interrupt enable bit A/D conversion/Timer 1 interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit) 0 : Interrupts disabled 1 : Interrupts enabled b7 Fig. 17 Structure of Interrupt-related registers Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 22 of 89 7547 Group Key Input Interrupt (Key-On Wake-Up) A key-on wake-up interrupt request is generated by applying "L" level to any pin of port P0 that has been set to input mode. In other words, it is generated when the AND of input level goes from "1" to "0". An example of using a key input interrupt is shown in Figure 18, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports P00 to P03 as input ports. Port PXx "L" level output PULL register bit 3 = "0" * P07 output ** Port P07 latch Falling edge detection Port P07 Direction register = "1" Key input interrupt request PULL register bit 3 = "0" * P06 output Port P06 key-on wakeup selection bit PULL register bit 3 = "0" * P05 output ** Port P05 latch ** Port P06 latch Port P06 Direction register = "1" Falling edge detection Port P05 Direction register = "1" Falling edge detection PULL register bit 3 = "0" * P04 output Port P04 key-on wakeup selection bit PULL register bit 2 = "1" * P03 input ** Port P03 latch ** Port P04 latch Port P04 Direction register = "1" Falling edge detection Port P03 Direction register = "0" Port P0 Input read circuit Falling edge detection PULL register bit 2 = "1" * P02 input ** Port P02 latch Port P02 Direction register = "0" Falling edge detection PULL register bit 1 = "1" * P01 input ** Port P01 latch Port P01 Direction register = "0" Falling edge detection PULL register bit 0 = "1" * P00 input Port P00 key-on wakeup selection bit ** Port P00 latch Port P00 Direction register = "0" Falling edge detection * P-channel transistor for pull-up ** CMOS output buffer Fig. 18 Connection example when using key input interrupt and port P0 block diagram Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 23 of 89 7547 Group Timers The 7547 Group has 4 timers: timer 1, timer X, timer A and timer B. The division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. All the timers are down count timers. When a timer reaches "0", an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. When a timer underflows, the interrupt request bit corresponding to each timer is set to "1". * Frequency divider for timer According to the clock division selection bits (b7 and b6) of CPU mode register (003B16), the count source of frequency divider is set as follows; b7b6 = "00"(high-speed), "01"(middle-speed), "11"(double-speed): XIN b7b6 = "10"(On-chip oscillator): On-chip oscillator qTimer X Timer X is an 8-bit timer and counts the prescaler X output. When Timer X underflows, the timer X interrupt request bit is set to "1". Prescaler X is an 8-bit prescaler and counts the signal selected by the timer X count source selection bit. Prescaler X and Timer X have the prescaler X latch and the timer X latch to retain the reload value, respectively. The value of prescaler X latch is set to Prescaler X when Prescaler X underflows.The value of timer X latch is set to Timer X when Timer X underflows. When writing to Prescaler X (PREX) is executed, the value is written to both the prescaler X latch and Prescaler X. When writing to Timer X (TX) is executed, the value is written to both the timer X latch and Timer X. When reading from Prescaler X (PREX) and Timer X (TX) is executed, each count value is read out. Timer X can be selected in one of 4 operating modes by setting the timer X operating mode bits of the timer X mode register. (1) Timer mode Prescaler X counts the count source selected by the timer X count source selection bits. Each time the count clock is input, the contents of Prescaler X is decremented by 1. When the contents of Prescaler X reach "0016", an underflow occurs at the next count clock, and the prescaler X latch is reloaded into Prescaler X and count continues. The division ratio of Prescaler X is 1/(n+1) provided that the value of Prescaler X is n. The contents of Timer X is decremented by 1 each time the underflow signal of Prescaler X is input. When the contents of Timer X reach "0016", an underflow occurs at the next count clock, and the timer X latch is reloaded into Timer X and count continues. The division ratio of Timer X is 1/(m+1) provided that the value of Timer X is m. Accordingly, the division ratio of Prescaler X and Timer X is 1/((n+1)(m+1)) provided that the value of Prescaler X is n and the value of Timer X is m. (2) Pulse output mode In the pulse output mode, the waveform whose polarity is inverted each time timer X underflows is output from the CNTR0 pin. The output level of CNTR0 pin can be selected by the CNTR0 active edge switch bit. When the CNTR0 active edge switch bit is "0", the output of CNTR0 pin is started at "H" level. When this bit is "1", the output is started at "L" level. Also, the inverted waveform of pulse output from CNTR0 pin can be output from TXOUT pin by setting "1" to the P03/TXOUT output valid bit. When using a timer in this mode, set the port P14 and P03 direction registers to output mode. (3) Event counter mode The timer A counts signals input from the P14/CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. The active edge of CNTR0 pin input signal can be selected from rising or falling by the CNTR0 active edge switch bit . qTimer 1 Timer 1 is an 8-bit timer and counts the prescaler output. When Timer 1 underflows, the timer 1 interrupt request bit is set to "1". Prescaler 1 is an 8-bit prescaler and counts the signal which is the oscillation frequency divided by 16. Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1 latch to retain the reload value, respectively. The value of prescaler 1 latch is set to Prescaler 1 when Prescaler 1 underflows. The value of timer 1 latch is set to Timer 1 when Timer 1 underflows. When writing to Prescaler 1 (PRE1) is executed, the value is written to both the prescaler 1 latch and Prescaler 1. When writing to Timer 1 (T1) is executed, the value is written to both the timer 1 latch and Timer 1. When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is executed, each count value is read out. Timer 1 always operates in the timer mode. Prescaler 1 counts the signal which is the oscillation frequency divided by 16. Each time the count clock is input, the contents of Prescaler 1 is decremented by 1. When the contents of Prescaler 1 reach "0016", an underflow occurs at the next count clock, and the prescaler 1 latch is reloaded into Prescaler 1 and count continues. The division ratio of Prescaler 1 is 1/(n+1) provided that the value of Prescaler 1 is n. The contents of Timer 1 is decremented by 1 each time the underflow signal of Prescaler 1 is input. When the contents of Timer 1 reach "0016", an underflow occurs at the next count clock, and the timer 1 latch is reloaded into Timer 1 and count continues. The division ratio of Timer 1 is 1/(m+1) provided that the value of Timer 1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is 1/((n+1)(m+1)) provided that the value of Prescaler 1 is n and the value of Timer 1 is m. Timer 1 cannot stop counting by software. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 24 of 89 7547 Group (4) Pulse width measurement mode In the pulse width measurement mode, the pulse width of the signal input to P14/CNTR0 pin is measured. The operation of Timer X can be controlled by the level of the signal input from the CNTR0 pin. When the CNTR0 active edge switch bit is "0", the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR0 pin is "H". The count is stopped while the pin is "L". Also, when the CNTR0 active edge switch bit is "1", the signal selected by the timer X count source selection bit is counted while the input signal level of CNTR0 pin is "L". The count is stopped while the pin is "H". Timer X can stop counting by setting "1" to the timer X count stop bit in any mode. Also, when Timer X underflows, the timer X interrupt request bit is set to "1". Note on Timer X is described below; s Note on Timer X (1) CNTR0 interrupt active edge selection-1 CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit. When this bit is "0", the CNTR0 interrupt request bit is set to "1" at the falling edge of CNTR0 pin input signal. When this bit is "1", the CNTR0 interrupt request bit is set to "1" at the rising edge of CNTR0 pin input signal. (2) CNTR0 interrupt active edge selection-2 According to the setting value of CNTR0 active edge switch bit, the interrupt request bit may be set to "1". When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. Set the corresponding interrupt enable bit to "0" (disabled). Set the active edge switch bit. Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. Set the corresponding interrupt enable bit to "1" (enabled). b7 b0 Timer X mode register (TXM : address 002B16, initial value: 0016) Timer X operating mode bits b1 b0 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR0 active edge switch bit 0 : Interrupt at falling edge Count at rising edge (in event counter mode) 1 : Interrupt at rising edge Count at falling edge (in event counter mode) Timer X count stop bit 0 : Count start 1 : Count stop P03/TXOUT output valid bit 0 : Output invalid (I/O port) 1 : Output valid (Inverted CNTR0 output) Not used (return "0" when read) Fig. 19 Structure of timer X mode register b7 b0 Timer count source set register (TCSS : address 002A16, initial value: 0016) Timer X count source selection bits b1 b0 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : f(XIN) (Note 1) 1 1 : Not available Timer A count source selection bits b4 b3 b2 0 0 0 : f(XIN)/16 0 0 1 : f(XIN)/2 0 1 0 : f(XIN)/32 0 1 1 : f(XIN)/64 1 0 0 : f(XIN)/128 1 0 1 : f(XIN)/256 1 1 0 : On-chip oscillator output (Note 2) 1 1 1 : Not available Timer B count source selection bits b7 b6 b5 0 0 0 : f(XIN)/16 0 0 1 : f(XIN)/2 0 1 0 : f(XIN)/32 0 1 1 : f(XIN)/64 1 0 0 : f(XIN)/128 1 0 1 : f(XIN)/256 1 1 0 : Timer A underflow 1 1 1 : Not available Notes 1: f(XIN) can be used as timer X count source when using a ceramic resonator or on-chip oscillator. Do not use it at RC oscillation. 2: On-chip oscillator can be used when the on-chip oscillator is enabled by bit 3 of CPUM. Fig. 20 Timer count source set register Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 25 of 89 7547 Group Data bus Prescaler 1 latch (8) Timer 1 latch (8) 1/16 Prescaler 1 (8) Timer 1 (8) Timer 1 interrupt request Clock division ratio selection bits "00" "01" "11" Frequency Timer X count source selection bits divider Data bus XIN On-chip "10" oscillator CPU mode register 1/16 1/2 1/1 Prescaler X latch (8) Pulse width measurement Timer mode Pulse output mode mode Prescaler X (8) Timer X latch (8) Timer X (8) P14/CNTR0 CNTR0 active edge switch bit "0" "1" Event counter mode Timer X interrupt request bit CNTR0 interrupt request bit Timer X count stop bit CNTR0 active "1" edge switch bit Q Q Toggle flip-flop T R Writing to timer X latch Pulse output mode Port P14 direction register Pulse output mode P03/TXOUT Port P14 latch "0" Port P03 latch P03/TXOUT output valid Port P03 direction register Fig. 21 Block diagram of timer 1 and timer X Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 26 of 89 7547 Group qTimer A,B Timer A and Timer B are 16-bit timers and counts the signal which is the oscillation frequency selected by setting of the timer count source set register (TCSS). Timer A and Timer B have the same function except of the count source clock selection. The count source clock of Timer A is selected from among 1/2,1/ 16, 1/32, 1/64, 1/128, 1/256 of f(XIN) clock and on-chip oscillator clock. The count source clock of Timer B is selected from among 1/2, 1/ 16, 1/32, 1/64, 1/128, 1/256 of f(XIN) clock and Timer A underflow. Timer A (B) consists of the low-order of Timer A: TAL (Timer B: TBL) and the high-order of Timer A: TAH (Timer B: TBH). Timer A (B) is decremented by 1 when each time of the count clock is input. When the contents of Timer A (B) reach "000016", an underflow occurs at the next count clock, and the timer latch is reloaded into timer. When Timer A (B) underflows, the Timer A (B) interrupt request bit is set to "1". Timer A (B) has the Timer A (B) latch to retain the load value. The value of timer A (B) latch is set to Timer A (B) at the timing of Timer A (B) underflow. The division ratio of Timer A (B) is 1/(n+1) provided that the value of Timer A (B) is n. When writing to both the low-order of Timer A (B) and the high order of Timer A (B) is executed, writing to "latch only" or "latch and timer" can be selected by the setting value of the timer A (B) write control bit. When reading from Timer A (B) register is executed, the count value of Timer A (B) is read out. Be sure to write to/read out the low-order of Timer A (B) and the high-order of Timer A (B) in the following order; * Read Read the high-order of Timer A (B) first, and the low-order of Timer A (B) next and be sure to read both high-order and low-order. * Write Write to the low-order of Timer A (B) first, and the high-order of Timer A (B) next and be sure to write both low-order and high order. Timer A and Timer B can be used for the timing timer of Input capture and Output compare function. s Notes on Timer A, B (1) Setting of timer value When "1: Write to only latch" is set to the timer A (B) write control bit, written data to timer register is set to only latch even if timer is stopped. Accordingly, in order to set the initial value for timer when it is stopped, set "0: Write to latch and timer simultaneously" to timer A (B) write control bit. (2) Read/write of timer A Stop timer A to read/write its data when the system is in the following state; * CPU operation clock source: XIN oscillation * Timer A count source: On-chip oscillator output (3) Read/write of timer B Stop timer B to read/write its data when the system is in the following state; * CPU operation clock source: XIN oscillation * Timer B count source: Timer A underflow * Timer A count source: On-chip oscillator output Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 27 of 89 7547 Group b7 b0 Timer A, B mode register (TABM : address 001D16, initial value: 0016) Timer A write control bit 0 : Write to latch and timer simultaneously 1 : Write to only latch Timer A count stop bit 0 : Count start 1 : Count stop Timer B write control bit 0 : Write to latch and timer simultaneously 1 : Write to only latch Timer B count stop bit 0 : Count start 1 : Count stop Not used (return "0" when read) Compare 0, 1 modulation mode bit 0: Disabled 1: Enabled Compare 2, 3 modulation mode bit 0: Disabled 1: Enabled b7 b0 Timer count source set register (TCSS : address 002A16, initial value: 0016) Timer X count source selection bits b1 b0 0 0 : f(XIN)/16 0 1 : f(XIN)/2 1 0 : f(XIN) (Note 1) 1 1 : Not available Timer A count source selection bits b4 b3 b2 0 0 0 : f(XIN)/16 0 0 1 : f(XIN)/2 0 1 0 : f(XIN)/32 0 1 1 : f(XIN)/64 1 0 0 : f(XIN)/128 1 0 1 : f(XIN)/256 1 1 0 : On-chip oscillator output (Note 2) 1 1 1 : Not available Timer B count source selection bits b7 b6 b5 0 0 0 : f(XIN)/16 0 0 1 : f(XIN)/2 0 1 0 : f(XIN)/32 0 1 1 : f(XIN)/64 1 0 0 : f(XIN)/128 1 0 1 : f(XIN)/256 1 1 0 : Timer A underflow 1 1 1 : Not available Notes 1: f(XIN) can be used as timer X count source when using a ceramic resonator or on-chip oscillator. Do not use it at RC oscillation. 2: On-chip oscillator can be used when the on-chip oscillator is enabled by bit 3 of CPUM. Fig. 22 Structure of timer A, B mode register Fig. 23 Timer count source set register Clock division ratio selection "00" bits "01" "11" XIN On-chip oscillator "10" CPU mode register Frequency divider 1/2 1/16 1/32 1/64 1/128 1/256 On-chip oscillator Data bus Timer A (low-order) latch (8) Timer A (high-order) latch (8) Timer A write control bit Timer A (low-order) (8) Timer A count source selection bits Timer A count stop bit Timer A (high-order) (8) Timer A interrupt request Compare Capture Frequency divider 1/2 1/16 1/32 1/64 1/128 1/256 Data bus Timer B (low-order) latch (8) Timer B (high-order) latch (8) Timer B write control bit Timer B (low-order) (8) Timer B count source selection bits Timer B count stop bit Timer B (high-order) (8) Timer B interrupt request Compare Capture Fig. 24 Block diagram of timer A and timer B Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 28 of 89 7547 Group Output compare 7547 group has 4-output compare channels. Each channel (0 to 3) has the same function and can be used to output waveform by using count value of either Timer A or Timer B. The source timer for each channel is selected by setting value of the compare x (x = 0, 1, 2, 3) timer source bit. Timer A and Timer B can be selected for the source timer to each channel, respectively. To use each compare channel, set "1" to the compare x output port bit and set the port direction register corresponding to compare channel to output mode. The compare value for each channel is set to the compare register (low-order) and compare register (high-order). Writing to the register for each channel is controlled by setting value of compare register write pointer. Writing to each register is in the following order; 1.Set the value of corresponded output compare channel to the compare register write pointer. 2.Write a value to the compare register (low-order) and compare register (high-order). 3.Set "1" to the compare latch y (y = 00, 01, 10, 11, 20, 21, 30, 31) re-load bit. When "1" is set to the compare latch y re-load bit, the value set to the compare register is loaded to compare latch when the next timer underflow. When count value of timer and setting value of compare latch is matched, compare output trigger occurs. When "1: Enabled" is set to the compare trigger x enable bit, the output waveform from port is inverted by compare trigger. When "0: Disabled" is set to the compare trigger x enable bit, the output waveform is not inverted, so port output can be fixed to "H" or "L". When "0: Positive" is set to the compare x output level latch, the compare output waveform is turned to "H level" at compare latch x0's match and turned to "L level" at compare latch x1's match. When "1 :Negative" is set to the compare x output level latch, the compare output waveform is turned to "L level" at compare latch x0's match and turned to "H level" at compare latch x1's match. The compare output level of each channel can be confirmed by reading the compare x output status bit. Compare output interrupt is available when match of each compare channel and timer count value. The interrupt request from each channel can be disabled or enabled by setting value of compare latch y interrupt source bit. Compare 0,1 (2,3) modulation mode In compare modulation mode, modulation waveform can be generated by using compare channel 0 and 1, or compare channel 2 and 3. To use this mode, * Set "1: Enabled" to the compare 0,1 (2, 3) modulation mode bit. * Set Timer A underflow for Timer B count source. * Set Timer A for the timer source of compare channel 0 (2). * Set Timer B for the timer source of compare channel 1 (3). In this mode, AND waveform of compare 0 (1) and compare 2 (3) is generated from Port P01 and P31, respectively. Accordingly, in order to use this mode, set "1" to the compare 0 output port bit or compare 2 output port bit. s Notes on Output Compare * When the selected source timer of each compare channel is stopped, written data to compare register is loaded to the compare latch simultaneously. * Do not write the same data to both of compare latch x0 and x1. * When setting value of the compare latch is larger than timer setting value, compare match signal is not generated. Accordingly, the output waveform is fixed to "L" or "H" level. However, when setting value of another compare latch is smaller than timer setting value, this compare match signal is generated. Accordingly, compare match interrupt occurs. * When the compare x trigger enable bit is cleared to "0" (disabled), the match trigger to the waveform output circuit is disabled, and the output waveform can be fixed to "L" or "H" level. However, in this case, the compare match signal is generated. Accordingly, compare match interrupt occurs. b7 b0 Capture/compare register R/W pointer (CCRP : address 001216, initial value: 0016) Compare register R/W pointer b2 b1 b0 0 0 0 : Compare latch 00 0 0 1 : Compare latch 01 0 1 0 : Compare latch 10 0 1 1 : Compare latch 11 1 0 0 : Compare latch 20 1 0 1 : Compare latch 21 1 1 0 : Compare latch 30 1 1 1 : Compare latch 31 Not used (returns "0" when read) Capture register 0 R/W pointer 0: Capture latch 00 1: Capture latch 01 Capture register 1 R/W pointer 0: Capture latch 10 1: Capture latch 11 Not used (returns "0" when read) Fig. 25 Structure of capture/compare register R/W pointer b7 b0 Compare register re-load register (CMPR : address 001416, initial value: 0016) Compare latch 00, 01 re-load bit 0: Re-load disabled 1: Re-load at next underflow Compare latch 10, 11 re-load bit 0: Re-load disabled 1: Re-load at next underflow Compare latch 20, 21 re-load bit 0: Re-load disabled 1: Re-load at next underflow Compare latch 30, 31 re-load bit 0: Re-load disabled 1: Re-load at next underflow Not used (returns "0" when read) Fig. 26 Structure of compare register re-load register Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 29 of 89 7547 Group b7 b0 Capture/Compare port register (CCPR : address 001E16, initial value: 0016) Capture 0 input port bits b1 b0 0 0: Capture from P00 0 1: Capture from P10 1 0: Ring/512 1 1: Not available Compare 0 output port bit 0: P01 is I/O port 1: P01 is Compare 0 Compare 1 output port bit 0: P02 is I/O port 1: P02 is Compare 1 Capture 1 input port bit 0: Capture from P30 1: Ring/512 Compare 2 output port bit 0: P31 is I/O port 1: P31 is Compare 2 Compare 3 output port bit 0: P32 is I/O port 1: P32 is Compare 3 Not used (returns "0" when read) b7 b0 Capture/Compare status register (CCSR : address 002216, initial value: 0016) Compare 0 output status bit 0: "L" level output 1: "H" level output Compare 1 output status bit 0: "L" level output 1: "H" level output Compare 2 output status bit 0: "L" level output 1: "H" level output Compare 3 output status bit 0: "L" level output 1: "H" level output Capture 0 status bit 0: latch 00 captured 1: latch 01 captured Capture 1 status bit 0: latch 10 captured 1: latch 11 captured Not used (returns "0" when read) Fig. 27 Structure of capture/compare port register b7 b0 Fig. 30 Structure of capture/compare status register b7 b0 Timer source selection register (TMSR : address 001F16, initial value: 0016) Compare 0 timer source bit Compare 1 timer source bit Compare 2 timer source bit Compare 3 timer source bit Capture 0 timer source bit Capture 1 timer source bit Not used (returns "0" when read) 0: Timer A 1: Timer B Compare interrupt source register (CISR : address 002316, initial value: 0016) Compare latch 00 interrupt source bit Compare latch 01 interrupt source bit Compare latch 10 interrupt source bit Compare latch 11 interrupt source bit Compare latch 20 interrupt source bit Compare latch 21 interrupt source bit Compare latch 30 interrupt source bit Compare latch 31 interrupt source bit Fig. 28 Structure of timer source selection register b7 b0 0: Disabled 1: Enabled Compare output mode register (CMOM : address 002116, initial value: 0016) Compare 0 output level latch 0: Positive 1: Negative Compare 1 output level latch 0: Positive 1: Negative Compare 2 output level latch 0: Positive 1: Negative Compare 3 output level latch 0: Positive 1: Negative Compare 0 trigger enable bit 0: Disabled 1: Enabled Compare 1 trigger enable bit 0: Disabled 1: Enabled Compare 2 trigger enable bit 0: Disabled 1: Enabled Compare 3 trigger enable bit 0: Disabled 1: Enabled Fig. 31 Structure of compare interrupt source register Fig. 29 Structure of compare output mode register Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 30 of 89 7547 Group Compare latch 00 Compare latch 01 P01/CMP0 Wave latch channel 0 Timer A counter Compare 0 timer source bit Timer B counter Compare channel 0 Timer B latch Timer A latch P02/CMP1 P31/CMP2 Compare channel 1 Compare channel 2 P32/CMP3 Compare channel 3 Fig. 32 Block diagram of output compare Data bus Compare register write pointer (001216, bits 0 to 2) Compare buffer 00 (16) Compare latch 00, 01 re-load bit (001416, bit 0) Compare latch 00 (16) Compare 0 output port bit (001E16, bit 2) I/O port Output latch P01/CMP0 Compare 0 output level latch (002116, bit 0) Compare interrupt Compare latch 00 interrupt source bit (002316, bit 0) Compare latch 01 interrupt source bit (002316, bit 1) Compare 0 timer source bit (001F16, bit 0) Timer A counter (16) Timer B counter (16) Compare 0 output status bit (002216, bit 0) Compare 0 trigger enable bit (002116, bit 4) Compare latch 01 (16) Compare register Compare buffer 01 (16) Fig. 33 Block diagram of compare channel 0 Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 31 of 89 7547 Group Data bus Compare register write pointer (001216, bits 0 to 2) Compare buffer 00 (16) Compare 0 output port bit (001E16, bit 2) Compare latch 00, 01 re-load bit (001416, bit 0) Compare latch 00 (16) Compare 0 output status bit (002216, bit 0) Compare 0 trigger enable bit (002116, bit 4) Compare latch 01 (16) Compare register Compare buffer 01 (16) P01/CMP0 I/O port Output latch Timer A counter (16) Compare 0 output level latch (002116, bit 0) Compare 0 (1) timer source bits (001F16, bit 0 (bit 1) Compare 1 output status bit (002216, bit 1) Compare 1 trigger enable bit (002116, bit 5) Timer B counter (16) Output latch Underflow Compare 1 output level latch (002116, bit 1) Compare latch 10 (16) Compare latch 10, 11 re-load bit (001416, bit 1) Compare buffer 10 (16) Compare register write pointer (001216, bits 0 to 2) Data bus Compare register Compare latch 11 (16) Compare buffer 11 (16) Fig. 34 Block diagram at modulation mode Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 32 of 89 7547 Group Timer count clock Timer underflow Re-load the count value Timer count value 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B Compare latch 00 Compare latch 01 Compare 00 match Compare 01 match Compare output Compare interrupt Compare status bit 0 1 0 000B 0005 Note: Compare interrupt occurs only for the interrupt source selected by Compare interrupt source register. Fig. 35 Output compare mode (general waveform) Timer count clock Timer underflow Re-load the count value Timer count value 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B Compare latch 00 Compare latch 01 Compare latch 00 write Compare latch 01 write Compare latch 00, 01 re-load bit Compare latch 00, 01 re-load signal 000B 0005 000E 000C Compare 00 match Compare 01 match Compare output Compare interrupt Compare status bit 0 1 0 1 0 Fig. 36 Output compare mode (compare register write timing) Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 33 of 89 7547 Group Carrier wave generated by Compare 0 Timer A count clock Timer A underflow Timer A count value 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 Compare latch 00 Compare latch 01 Compare 00 match Compare 01 match Compare 0 output Compare 0 output status bit 1 0 1 0 1 0006 0002 Modulation of output waveform generated by Compare 1 Timer A underflow Compare 0 output Timer B count value 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 Compare latch 10 Compare latch 11 Compare 10 match Compare 11 match Compare 1 output Compare interrupt Compare 1 output status bit 0 1 0 1 0 1 0004 0001 Port outptu wavefowm Modulation output Note: Compare interrupt occurs only for the interrupt source selected by Compare interrupt source register. Fig. 37 Output compare mode (compare 0, 1 modulation mode) Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 34 of 89 7547 Group 1. When Compare 0 output level latch is "Positive", Compare 1 output level latch is "Positive". Compare 0 output Compare 1 output Modulation output 2. When Compare 0 output level latch is "Negative", Compare 1 output level latch is "Positive". Compare 0 output Compare 1 output Modulation output 3. When Compare 0 output level latch is "Positive", Compare 1 output level latch is "Negative". Compare 0 output Compare 1 output Modulation output 4. When Compare 0 output level latch is "Negative", Compare 1 output level latch is "Negative". Compare 0 output Compare 1 output Modulation output Fig. 38 Output compare mode (compare 0, 1 modulation mode: effect of output level latch) Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 35 of 89 7547 Group Input capture 7547 group has 2-input capture channels. Each channel (0 and 1) has the same function and can be used to capture count value of either Timer A or Timer B. The source timer for each channel is selected by setting value of the capture x (x = 0, 1) timer source bit. Timer A and Timer B can be selected for the source timer to each channel, respectively. To use each capture channel, set the capture x input port bits and set the port direction register corresponding to capture channel to input mode. The input capture circuit retains the count value of selected timer when external trigger is input. The timer count value is retained to the capture latch x0 when rising edge is input and is retained to the capture latch x1 when falling edge is input. The count value of timer can be retained by software by capture y (y = 00, 01, 10, 11) software trigger bit too. When "1" is set to this bit, count value of timer is retained to the corresponded capture latch. When reading from the capture y software trigger bit is executed, "0" is read out. The latest status of capture latch can be confirmed by reading of the capture x status bit. This bit indicates the capture latch which latest data is in. The valid trigger edge for capture interrupt is set by the capture x interrupt edge selection bits. (Regardless of the setting value of capture x interrupt edge selection bits, timer count values for both edges are retained to the capture latch.) Each capture input has the noise filter circuit that judges continuous 4-time same level with sampling clock to be valid. The sampling clock of noise filter is set by the capture x noise filter clock selection bits. Reading from the register for each channel is controlled by setting value of the capture register read pointer. Reading from each register is in the following order; 1.Set the value of the corresponded input capture channel to the capture register read pointer. 2.Read from the capture register (low-order) and capture register (high-order). s Notes on Input Capture * If the capture trigger is input while the capture register (low-order and high-order) is in read, captured value is changed between high-order reading and low-order reading. Accordingly, some countermeasure by program is recommended, for example comparing the values that twice of read. * When CPU operation clock source is XIN oscillation and the onchip-oscillator is selected for Timer A count source, Timer A cannot be used for the capture source timer. Timer B cannot be used for the capture source timer when the system is in the following state; * CPU operation clock source: XIN oscillation * Timer B count source: Timer A underflow * Timer A count source: On-chip oscillator output * When writing "1" to capture latch x0 (x1) software trigger bit of capture latch x0 and x1 at the same time, or external trigger and software trigger occur simultaneously, the set value of capture x status bit is undefined. * When setting the interrupt active edge selection bit and noise filter clock selection bit of external interrupt CAP0, CAP1, the interrupt request bit may be set to "1". When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. Set the corresponding interrupt enable bit to "0" (disabled). Set the interrupt edge selection bit or noise filter clock selection bit. Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. Set the corresponding interrupt enable bit to "1" (enabled). * When the capture interrupt is used as the interrupt for return from stop mode, set the capture x noise filter clock selection bits to "00 (Filter stop)". Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 36 of 89 7547 Group b7 b0 b7 b0 Capture register 0 (Low-order) (CAP0L : address 000C16) b7 b0 Capture software trigger register (CSTR : address 001316, initial value: 0016) Capture latch 00 software trigger bit Capture latch 01 software trigger bit Capture register 0 (High-order) (CAP0H : address 000D16) b7 b0 Capture latch 10 software trigger bit Capture latch 11 software trigger bit Capture register 1 (Low-order) (CAP1L : address 000E16) b7 b0 Each software trigger occurs by setting "1" to corresponding bit. (returns "0" when read) Not used (returns "0" when read) Capture register 1 (High-order) (CAP1H : address 000F16) b7 b0 Fig. 39 Structure of capture software trigger register Capture mode register (CAPM : address 002016, initial value: 0016) Capture 0 interrupt edge selection bits b1 b0 0 0: Rising and falling edge 0 1: Rising edge 1 0: Falling edge 1 1: Not available Capture 1 interrupt edge selection bits b3 b2 0 0: Rising and falling edge 0 1: Rising edge 1 0: Falling edge 1 1: Not available Capture 0 noise filter clock selection bits b5 b4 0 0: Filter stop 0 1: f(XIN) 1 0: f(XIN)/8 1 1: f(XIN)/32 Capture 1 noise filter clock selection bits b7 b6 0 0: Filter stop 0 1: f(XIN) 1 0: f(XIN)/8 1 1: f(XIN)/32 Fig. 40 Structure of capture software trigger register/capture mode register Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 37 of 89 7547 Group P00/CAP0 Trigger input channel 0 P10/CAP0 Ring /512 Capture 0 timer source bit Timer B counter P30/CAP1 Capture channel 0 Ring /512 Timer B latch Capture latch 00 Capture latch 01 Timer A latch Timer A counter Capture channel 1 Fig. 41 Block diagram of input capture Data bus Capture register 0 read pointer (001216, bit 4) Capture latch 00 (16) Capture 0 status bit (002216, bit 4) Capture latch 00 software trigger bit (001316, bit 0) Ring/512 Digital filter P10/CAP0 P00/CAP0 Capture 0 input port bits (001E16, bits 0, 1) Capture 0 noise filter clock selection bits (002016, bits 4, 5) Capture trigger Capture latch 0 (16) Capture register Capture latch 01 (16) Capture pointer (001216, bits 4, 5) Rising Falling Capture 0 interrupt edge selection bits (002016, bits 0, 1) Capture interrupt Capture 0 timer source bit (001F16, bit 4) Timer A counter (16) Timer B counter (16) Fig. 42 Block diagram of capture channel 0 Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 38 of 89 7547 Group Re-load the timer count value Timer underflow Capture input wave Timer count value 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B Overwrite Capture latch 00 Capture latch 01 Capture interrupt Capture x (x=0, 1) status bit 1 0 1 0 1 0 XXXX XXXX 000A 0005 0001 000F 000C Fig. 43 Capture interrupt edge selection = "rising edge" Re-load the timer count value Timer underflow Capture input wave Timer count value 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B Overwrite Capture latch 00 Capture latch 01 Capture interrupt Capture x (x=0, 1) status bit 1 0 1 0 1 0 XXXX XXXX 000A 0005 0001 000F 000C Fig. 44 Capture interrupt edge selection = "rising and falling edge" Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 39 of 89 7547 Group Serial Interface The 7547 Group has Serial I/O1 and Serial I/O2. Except that Serial I/O1 has the bus collision detection function and the TXD2 output structure for Serial I/O2 is CMOS only, they have the same function. qSerial I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Data bus (1) Clock Synchronous Serial I/O1 Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6) to "1". For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. Address 001816 Receive buffer register 1 Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit P10/RXD1/CAP0 Receive shift register 1 Shift clock P12/SCLK1 Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1 Address 001C16 1/4 XIN BRG count source selection bit 1/4 P13/SRDY1 F/F Falling-edge detector Shift clock Clock control circuit Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 P11/TXD1 Transmit shift register 1 Transmit buffer register 1 Address 001816 Data bus Fig. 45 Block diagram of clock synchronous serial I/O1 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD1 Serial input RxD1 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY1 Write pulse to receive/transmit buffer register 1 (address 001816) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD1 pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" . Fig. 46 Operation of clock synchronous serial I/O1 function Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 40 of 89 7547 Group (2) Asynchronous Serial I/O1 (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 001816 Receive buffer register 1 OE Character length selection bit ST detector 7 bits Receive shift register 1 Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 P10/RXD1/CAP0 8 bits PE FE SP detector Clock control circuit Serial I/O1 synchronous clock selection bit P12/SCLK1 BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator 1 Address 001C16 1/4 ST/SP/PA generator 1/16 P11/TXD1 Character length selection bit Transmit buffer register 1 Transmit shift register 1 UART1 control register Address 001B16 XIN Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Address 001816 Data bus Fig. 47 Block diagram of UART serial I/O1 Transmit or receive clock Transmit buffer 1 write signal TBE=0 TSC=0 TBE=1 Serial output TXD1 ST TBE=0 TBE=1 TSC=1 D0 D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1 SP Generated at 2nd bit in 2-stop-bit mode Receive buffer 1 read signal RBF=0 RBF=1 RBF=1 Serial input RXD1 ST D0 D1 SP ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1," can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1." 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 48 Operation of UART serial I/O1 function Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 41 of 89 7547 Group [Transmit buffer register 1/receive buffer register 1 (TB1/ RB1)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Serial I/O1 status register (SIO1STS)] 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O1 enable bit SIOE (bit 7 of the serial I/O1 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O1 status register are initialized to "0" at reset, but if the transmit enable bit of the serial I/O1 control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". [Serial I/O1 control register (SIO1CON)] 001A16 The serial I/O1 control register consists of eight control bits for the serial I/O1 function. [UART1 control register (UART1CON)] 001B16 The UART1 control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P11/TxD1 pin. [Baud rate generator 1 (BRG1)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. s Notes on Serial I/O1 * Serial I/O interrupt When setting the transmit enable bit to "1", the serial I/O transmit interrupt request bit is automatically set to "1". When not requiring the interrupt occurrence synchronized with the transmission enabled, take the following sequence. Set the serial I/O transmit interrupt enable bit to "0" (disabled). Set the transmit enable bit to "1". Set the serial I/O transmit interrupt request bit to "0" after 1 or more instructions have been executed. Set the serial I/O transmit interrupt enable bit to "1" (enabled). * I/O pin function when serial I/O1 is enabled. The functions of P12 and P13 are switched with the setting values of a serial I/O1 mode selection bit and a serial I/O1 synchronous clock selection bit as follows. (1) Serial I/O1 mode selection bit "1" : Clock synchronous type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit "0" : P12 pin turns into an output pin of a synchronous clock. "1" : P12 pin turns into an input pin of a synchronous clock. Setup of a SRDY1 output enable bit (SRDY) "0" : P13 pin can be used as a normal I/O pin. "1" : P13 pin turns into a SRDY1 output pin. (2) Serial I/O1 mode selection bit "0" : Clock asynchronous (UART) type serial I/O is selected. Setup of a serial I/O1 synchronous clock selection bit "0": P12 pin can be used as a normal I/O pin. "1": P12 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P13 pin. It can be used as a normal I/O pin. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 42 of 89 7547 Group b7 b0 Serial I/O1 status register (SIO1STS : address 001916, initial value: 8016) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) b7 b0 Serial I/O1 control register (SIO1CON : address 001A16, initial value: 0016) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY1 output enable bit (SRDY) 0: P13 pin operates as ordinary I/O pin 1: P13 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P10 to P13 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P10 to P13operate as serial I/O pins) b7 b0 UART1 control register (UART1CON : address 001B16, initial value: E016) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P11/TXD1 P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read) Fig. 49 Structure of serial I/O1-related registers Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 43 of 89 7547 Group Bus collision detection (SIO1) SIO1 can detect a bus collision by setting UART1 bus collision detection interrupt enable bit. When transmission is started in the clock synchronous or asynchronous (UART) serial I/O mode, the transmit pin TxD1 is compared with the receive pin RxD1 in synchronization with rising edge of transmit shift clock. If they do not coincide with each other, a bus collision detection interrupt request occurs. When a transmit data collision is detected between LSB and MSB of transmit data in the clock synchronous serial I/O mode or between the start bit and stop bit of transmit data in UART mode, a bus collision detection can be performed by both the internal clock and the external clock. A block diagram is shown in Fig. 51. A timing diagram is shown in Fig. 52. b7 b0 Interrupt source set register (INTSET: address 000A16, initial value: 0016) Key-on wakeup interrupt valid bit UART1 bus collision detection interrupt valid bit A/D conversion interrupt valid bit Timer 1 interrupt valid bit Not used (returns "0" when read) 0: Interrupt invalid 1: Interrupt valid b7 b0 Interrupt source discrimination register (INTDIS: address 000B16, initial value: 0016) Key-on wakeup interrupt discrimination bit UART1 bus collision detection interrupt discrimination bit A/D conversion interrupt discrimination bit Timer 1 interrupt discrimination bit Not used (returns "0" when read) 0: Interrupt does not occur 1: Interrupt occurs b7 b0 Interrupt request register 1 (IREQ1 : address 003C16, initial value : 0016) Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Serial I/O2 receive interrupt request bit Serial I/O2 transmit interrupt request bit INT0 interrupt request bit INT1 interrupt request bit Key-on wake up/UART1 bus collision detection interrupt request bit CNTR0 interrupt request bit 0 : No interrupt request issued 1 : Interrupt request issued Note: Bus collision detection can be used when SIO1 is operating at full-duplex communication. When SIO1 is operating at half-duplex communication, set bus collision detection interrupt to be disabled. b7 b0 Interrupt control register 1 (ICON1 : address 003E16, initial value : 0016) Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Serial I/O2 receive interrupt enable bit Serial I/O2 transmit interrupt enable bit INT0 interrupt enable bit INT1 interrupt enable bit Key-on wake up/UART1 bus collision detection interrupt enable bit CNTR0 interrupt enable bit 0 : Interrupts disabled 1 : Interrupts enabled Fig. 50 Bus collision detection circuit related registers UART1 bus collision detection interrupt discrimination bit (Address 000B16, bit 1) TxD1 RxD1 D Q Key-on wakeup/ UART1 bus collision detection interrupt request bit (Address 003C16, bit 6) Key-on wakeup interrupt request UART1 bus collision detection interrupt valid bit (Address 000A16, bit 1) Shift clock Fig. 51 Block diagram of bus collision detection interrupt circuit Transmit shift clock Transmit pin TxD1 Receive pin RxD1 Data collision Bus collision detection interrupt generation Fig. 52 Timing diagram of bus collision detection interrupt Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 44 of 89 7547 Group qSerial I/O2 Serial I/O2 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O2 Mode Clock synchronous serial I/O2 mode can be selected by setting the serial I/O2 mode selection bit of the serial I/O2 control register (bit 6) to "1". For clock synchronous serial I/O2, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. Data bus Address 002E16 Receive buffer register 2 Serial I/O2 control register Address 003016 Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuit P04/RXD2 Receive shift register 2 Shift clock P06/SCLK2 XIN BRG count source selection bit 1/4 Serial I/O2 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 2 Address 003216 1/4 P07/SRDY2 F/F Falling-edge detector Shift clock Clock control circuit Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O2 status register Address 002F16 P05/TXD2 Transmit shift register 2 Transmit buffer register 2 Address 002E16 Data bus Fig. 53 Block diagram of clock synchronous serial I/O2 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD2 Serial input RxD2 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY2 Write pulse to receive/transmit buffer register 2 (address 002E16) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O2 control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD2 pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" . Fig. 54 Operation of clock synchronous serial I/O2 function Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 45 of 89 7547 Group (2) Asynchronous Serial I/O2 (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O2 mode selection bit of the serial I/O2 control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Address 002E16 Receive buffer register 2 OE Character length selection bit ST detector 7 bits Receive shift register 2 Serial I/O2 control register Address 003016 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 P04/RXD2 8 bits PE FE SP detector Clock control circuit Serial I/O2 synchronous clock selection bit P06/SCLK2 BRG count source selection bit Frequency division ratio 1/(n+1) Baud rate generator 2 Address 003216 1/4 ST/SP/PA generator 1/16 P05/TXD2 Character length selection bit Transmit buffer register 2 Transmit shift register 2 UART2 control register Address 003116 XIN Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O2 status register Address 002F16 Address 002E16 Data bus Fig. 55 Block diagram of UART serial I/O2 Transmit or receive clock Transmit buffer 2 write signal TBE=0 TSC=0 TBE=1 Serial output TXD2 ST TBE=0 TBE=1 TSC=1 D0 D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1 SP Generated at 2nd bit in 2-stop-bit mode Receive buffer 2 read signal RBF=0 RBF=1 RBF=1 Serial input RXD2 ST D0 D1 SP ST D0 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1," can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O2 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1." 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 56 Operation of UART serial I/O2 function Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 46 of 89 7547 Group [Transmit buffer register 2/receive buffer register 2 (TB2/ RB2)] 002E16 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Serial I/O2 status register (SIO2STS)] 002F16 The read-only serial I/O2 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O2 function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O2 enable bit SIOE (bit 7 of the serial I/O2 control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O2 status register are initialized to "0" at reset, but if the transmit enable bit of the serial I/O2 control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". [Serial I/O2 control register (SIO2CON)] 003016 The serial I/O2 control register consists of eight control bits for the serial I/O2 function. [UART2 control register (UART2CON)] 003116 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. [Baud rate generator 2 (BRG2)] 003216 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. s Notes on Serial I/O2 * Serial I/O interrupt When setting the transmit enable bit to "1", the serial I/O transmit interrupt request bit is automatically set to "1". When not requiring the interrupt occurrence synchronized with the transmission enabled, take the following sequence. Set the serial I/O transmit interrupt enable bit to "0" (disabled). Set the transmit enable bit to "1". Set the serial I/O transmit interrupt request bit to "0" after 1 or more instructions have been executed. Set the serial I/O transmit interrupt enable bit to "1" (enabled). * I/O pin function when serial I/O2 is enabled. The functions of P06 and P07 are switched with the setting values of a serial I/O2 mode selection bit and a serial I/O2 synchronous clock selection bit as follows. (1) Serial I/O2 mode selection bit "1" : Clock synchronous type serial I/O is selected. Setup of a serial I/O2 synchronous clock selection bit "0" : P06 pin turns into an output pin of a synchronous clock. "1" : P06 pin turns into an input pin of a synchronous clock. Setup of a SRDY2 output enable bit (SRDY) "0" : P07 pin can be used as a normal I/O pin. "1" : P07 pin turns into a SRDY2 output pin. (2) Serial I/O2 mode selection bit "0" : Clock asynchronous (UART) type serial I/O is selected. Setup of a serial I/O2 synchronous clock selection bit "0": P06 pin can be used as a normal I/O pin. "1": P06 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P07 pin. It can be used as a normal I/O pin. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 47 of 89 7547 Group b7 b0 Serial I/O2 status register (SIO2STS : address 002F16, initial value: 8016) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) b7 b0 Serial I/O2 control register (SIO2CON : address 003016, initial value: 0016) BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O2 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY2 output enable bit (SRDY) 0: P07 pin operates as ordinary I/O pin 1: P07 pin operates as SRDY2 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O2 mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O2 enable bit (SIOE) 0: Serial I/O2 disabled (pins P04 to P07 operate as ordinary I/O pins) 1: Serial I/O2 enabled (pins P04 to P07 operate as serial I/O pins) b7 b0 UART2 control register (UART2CON : address 003116, initial value: E016) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits Not used (return "0" when read) (Do not write "1" to this bit.) Not used (return "1" when read) Fig. 57 Structure of serial I/O2-related registers Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 48 of 89 7547 Group A/D Converter The functional blocks of the A/D converter are described below. [A/D conversion register] AD The A/D conversion register is a read-only register that stores the result of A/D conversion. Do not read out this register during an A/ D conversion. [A/D control register] ADCON The A/D control register controls the A/D converter. Bit 2 to 0 are analog input pin selection bits. Bit 3 is the A/D conversion clock selection bit. When "0" is set to this bit, the A/D conversion clock is f(XIN)/2 and the A/D conversion time is 122 cycles of f(XIN). When "1" is set to this bit, the A/D conversion clock is f(XIN) and the A/D conversion time is 61 cycles of f(XIN). Bit 4 is the A/D conversion completion bit. The value of this bit remains at "0" during A/D conversion, and changes to "1" at completion of A/D conversion. A/D conversion is started by setting this bit to "0". [Comparison voltage generator] The comparison voltage generator divides the voltage between AVSS and VREF by 1024, and outputs the divided voltages. [Channel selector] The channel selector selects one of ports P27/AN7 to P20/AN0, and inputs the voltage to the comparator. [Comparator and control circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage and stores its result into the A/D conversion register. When A/D conversion is completed, the control circuit sets the A/D conversion completion bit and the A/D interrupt request bit to "1". Because the comparator is constructed linked to a capacitor, set f(XIN) in order that the A/D conversion clock is 250 kHz or over during A/D conversion. s Notes on A/D converter As for AD translation accuracy, on the following operating conditions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value.. (2) When VREF voltage is lower than [ 3.0 V ], the accuracy at the low temperature may become extremely low compared with that at room temperature. When the system would be used at low temperature, the use at VREF=3.0 V or more is recommended. b7 b0 A/D control register (ADCON : address 003416, initial value: 1016) Analog input pin selection bits 000 : P20/AN0 001 : P21/AN1 010 : P22/AN2 011 : P23/AN3 100 : P24/AN4 101 : P25/AN5 110 : P26/AN6 111 : P27/AN7 A/D conversion clock selection bit (Note 1) 0 : f(XIN)/2 1 : f(XIN) A/D conversion completion bit 0 : Conversion in progress 1 : Conversion completed Not used (returns "0" when read) Notes 1: A/D conversion clock=f(XIN) can be used only when ceramic oscillation or on-chip oscillator is used. Select f(XIN)/2 when RC oscillation is used. Fig. 58 Structure of A/D control register Read 8-bit (Read only address 003516) b7 (Address 003516) b9 b8 b7 b6 b5 b4 b3 b0 b2 Read 10-bit (read in order address 003616, 003516) b7 (Address 003616) b7 (Address 003516) b7 b6 b5 b4 b3 b2 b1 b9 b0 b8 b0 b0 Note: High-order 6-bit of address 003616 returns "0" when read. Fig. 59 Structure of A/D conversion register Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 49 of 89 7547 Group Data bus b7 A/D control register (Address 003416) 3 P20/AN0 P21/AN1 P22/AN2 P23/AN3 P24/AN4 P25/AN5 P26/AN6 P27/AN7 f(XIN) f(XIN)/2 VREF A/D control circuit Channel selector b0 A/D interrupt request Comparator A/D conversion register (high-order) A/D conversion register (low-order) 10 Resistor ladder (Address 003616) (Address 003516) VSS Fig. 60 Block diagram of A/D converter Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 50 of 89 7547 Group Watchdog Timer The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of an 8-bit watchdog timer H and an 8-bit watchdog timer L, being a 16-bit counter. q Standard operation of watchdog timer (1) Start of watchdog timer The watchdog timer starts operating by setting value of the function set ROM data 2 (FSROM2: address 0FFA16) or writing to the watchdog timer control register (WDTCON: address 003916). Set "0" to the watchdog timer start selection bit (bit 1 of FSROM2) when operation starts by setting value of FSROM2. In this case, the watchdog timer starts operating after releasing reset. Write an arbitrary value to WDTCON when FSROM2 is set to be invalid and operation starts by program. Operation by program can start even when "1" (stop state after releasing reset) is set to the watchdog timer start selection bit. (2) Operation of watchdog timer Watchdog timer L is set to "FF16"and watchdog timer H is set to "FF16" by reset or writing an arbitrary value to WDTCON. When the watchdog timer starts operating, the selected clock is counted and internal reset occurs by the watchdog timer H underflow. Accordingly, write to WDTCON before underflow by program. When WDTCON is read, the values of the STP instruction function selection bit, watchdog timer H count source selection bit and the high-order 6 bits of the watchdog timer H are read. (3) Count source clock of watchdog timer The count source clock of the watchdog timer can be selected by the watchdog timer source clock selection bit (bit 0 of FSROM2). If "0" is set to the watchdog timer source clock selection bit, the count source clock of the watchdog timer always is the on-chip oscillator output/16. It changes by setting the clock division ratio selection bits (bit 7 and bit 6 of the CPU mode register) when "1" is set to the watchdog timer source clock selection bit or FSROM2 is set to be invalid. When a double-speed mode, a high-speed mode, and a middlespeed mode are selected by the clock division ratio selection bits, the count source clock of the watchdog timer becomes f(XIN)/16. When the supply from on-chip oscillator is selected, it becomes the on-chip oscillator output/16. (4) Watchdog timer H count source selection bit The count source of watchdog timer H can be selected by FSROM2 or program. When "0" is set to watchdog timer H count source selection bit (bit 2 of FSROM2), the watchdog timer L underflow signal is selected as the count source of watchdog timer H and the detection time is 131.072 ms at f(XIN) = 8 MHz. When "1" is set to this bit, the clock selected as the count source of watchdog timer L is input to watchdog timer H. In this case, the detection time is 512 s at f(XIN) =8 MHz. When FSROM2 is set to be invalid, the count source of watchdog timer can be set by watchdog timer H count source selection bit (bit 7 of WDTCON). When "0" is set to this bit, the watchdog timer L underflow signal is selected as the count source of watchdog timer H. When "1" is set to this bit, the clock selected as the count source of watchdog timer L is input to watchdog timer H. This bit is cleared to "0" after reset. (5) STP instruction function selection bit The function of the STP instruction can be selected by FSROM2 or program. When "0" is set to the STP instruction function selection bit (bit 3 of FSROM2), system enters into the stop mode at the STP instruction execution. When "1" is set to this bit, internal reset occurs at the STP instruction execution. When the function of the STP instruction is set by FSROM2, it cannot be changed by program. When setting value of FSROM2 is invalid, the function of the STP instruction can be set by the STP instruction function selection bit (bit 6 of WDTCON). When "0" is set to this bit, system enters into the stop mode at the STP instruction execution. When "1" is set to this bit, internal reset occurs at the STP instruction execution. Once this bit is set to "1", it cannot be changed to "0" by program. This bit is cleared to "0" after reset. s Notes on watchdog timer 1. The watchdog timer is operating during the wait mode. Write data to the watchdog timer control register to prevent timer underflow. 2. The watchdog timer stops during the stop mode. However, the watchdog timer is running during the oscillation stabilizing time after the STP instruction is released. In order to avoid the underflow of the watchdog timer, the watchdog timer count source selection bit (bit 7 of watchdog timer control register (address 3916)) before executing the STP instruction. 3. The STP instruction function selection bit (bit 6 of watchdog timer control register (address 3916)) can be rewritten only once after releasing reset. After rewriting it is disable to write any data to this bit. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 51 of 89 7547 Group Source clock selection (auto-switch depending on setting of CPUM) On-chip oscillator output can be fixed by bit 0 of FSROM2 Watchdog timer H count source selection bit (bit 2 of FSROM2) or bit 7 of WDTCON Write "FF16" to WDTCON Watchdog timer L (8) 1/16 "0" Watchdog timer H (8) "1" Data bus Write "FF16" to WDTCON XIN clock On-chip oscillator Count start (Watchdotm timer start selection bit (bit 1 of FSROM2)) or writing arbitrary value to WDTCON STP instruction function selection bit (bit 3 of FSROM2) Bit 6 of WDTCON STP Instruction Reset pin input FSROM2: Function set ROM data 2 WDTCON: Watchdog timer control register CPUM: CPU mode register Reset circuit Internal reset Fig. 61 Block diagram of watchdog timer b7 b0 Watchdog timer control register (Note 1) (WDTCON: address 003916, initial value: 3F16) Watchdog timer H (read only for high-order 6-bit) STP instruction function selection bit (Note 1, Note 3) 0 : System enters into the stop mode at the STP instruction execution 1 : Internal reset occurs at the STP instruction execution Watchdog timer H count source selection bit (Note 1, Note 4) 0 : Watchdog timer L underflow 1 : On-chip oscillator/16 or f(XIN)/16 Control by Function set ROM data 2 (FSROM2: address FFDA16) (Note 2) This cannot be controlled by FSROM2. This bit function can be set by setting bit 3 of FSROM2. Bit 3 of FSROM2 = 0: Bit 6 of WDTCON is fixed to "0". Bit 3 of FSROM2 = 1: Bit 6 of WDTCON is fixed to "1". The initial value of this bit is changed by setting bit 2 of FSROM2. Bit 2 of FSROM2 = 0: Initial value of bit 7 of WDTCON is changed to "0". Bit 2 of FSROM2 = 1: Initial value of bit 7 of WDTCON is changed to "1". The following setting can be available by setting bit 0 of FSROM2. (This setting cannot be set by WDTCON) Bit 0 of FSROM2 = 0: The source clock of watchdog timer is always the on-chip oscillator output/16. Bit 0 of FSROM2 = 1: The source clock of watchdog timer is the on-chip oscillator output/16 of f(XIN)/16. Notes 1: When the setting by the function set ROM data 2 (FSROM2) is performed, the initial value of CPUM is changed after releasing reset since bits 6 and 7 of WDTCON are fixed. 2: The setting values of FSROM2 become valid by setting "0" to bit 0 of function set ROM data 0 (FSROM0). The setting values of FSROM2 are invalid by setting "1" to this bit. 3:The setting value of this bit can be fixed after releasing reset by FSROM2, and then, the setting value cannot be changed by program. Also, when the setting by program is performed, this bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to this bit. 4: When FSROM2 is used to select the watchdog timer H count source, the initial value of this bit is changed after releasing reset. Fig. 62 Structure of watchdog timer control register Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 52 of 89 7547 Group Power-on Reset Circuit Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. In order to use the power-on reset circuit effectively, the time for the supply voltage to rise from 0 V to 1.8 V must be set to 1 ms or less. ____________ When the built-in power-on reset circuit is used, pull-up the RESET pin to VCC. 1 ms or les s VCC (Note) Power-on reset circuit output Low voltage Detection Circuit The built-in low voltage detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the power source voltage drops below a set value (Typ.1.90 V). The low voltage detection circuit is valid by setting "1" to bit 1 of the function set ROM data 0. Also, when "1" is set to bit 3 of the function set ROM data 0, the low voltage detection circuit can be valid even in the stop mode. The low voltage detection circuit is stopped in the stop mode by setting "0" to this bit, so that the power dissipation is reduced. Internal reset signal Reset state Power-on Reset released Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Fig. 63 Operation waveform diagram of power-on reset circuit VCC Reset voltage (Typ:1.90V) Internal reset signal Microcomputer starts operation by the built-in on-chip oscillator. Fig. 64 Operation waveform diagram of low voltage detection circuit On-chip oscillator clock RING Internal CPU clock RESET Internal reset signal SYNC Address Data ? ? ? ? ? ? ? ? ? ? FFFC ADL FFFD ADH,ADL ADH Reset address from the vector table 9 to 16 cycles of internal CPU clock Fig. 65 Timing diagram at reset Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 53 of 89 7547 Group Address (1) Port P0 direction register (P0D) (2) Port P1 direction register (P1D) (3) Port P2 direction register (P2D) (4) Port P3 direction register (P3D) (5) Interrupt source set register (INTSET) (6) Interrupt source discrimination register (INTDIS) (7) Compare register (low-order) (CMPL) (8) Compare register (high-order) (CMPH) (9) Capture/Compare register R/W pointer (CCRP) (10) Capture software trigger register (CSTR) (11) Compare register re-load register (CMPR) (12) Port P0P3 drive capacity control register (DCCR) (13) Pull-up control register (PULL) (14) Port P1P3 control register (P1P3C) (15) Serial I/O1 status register (SIO1STS) (16) Serial I/O1 control register (SIO1CON) (17) UART1 control register (UART1CON) (18) Timer A, B mode register (TABM) (19) Capture/Compare port register (CCPR) (20) Timer source selection register (TMSR) (21) Capture mode register (CAPM) (22) Compare output mode register (CMOM) (23) Capture/Compare status register (CCSR) (24) Compare interrupt source register (CISR) (25) Timer A (low-order) (TAL) (26) Timer A (high-order) (TAH) (27) Timer B (low-order) (TBL) (28) Timer B (high-order) (TBH) (29) Prescaler 1 (PRE1) (30) Timer 1 (T1) (31) Timer count source set register (TCSS) (32) Timer X mode register (TXM) (33) Prescaler X (PREX) (34) Timer X (TX) (35) Serial I/O2 control register (SIO2STS) (36) Serial I/O2 register (SIO2CON) (37) UART2 control register (UART2CON) (38) A/D control register (ADCON) 000116 000316 000516 000716 000A16 000B16 001016 001116 001216 001316 001416 001516 001616 001716 001916 001A16 001B16 001D16 001E16 001F16 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002F16 003016 003116 003416 1 0 0 1 1 1 Register contents 0016 X X X 0 0 0 0 0 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0 0 0 0 0 0 0 0016 1 1 0 0 0 0 0 0016 0016 0016 0016 0016 0016 0016 FF16 FF16 FF16 FF16 FF16 0116 0016 0016 FF16 FF16 0 0 0 0 0 0 0 0016 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 (39) On-chip oscillation division ratio selection register (RODR) 003716 003816 (40) MISRG (41) Watchdog timer control register (WDTCON) (Note 3) (42) Interrupt edge selection register (INTEDGE) (43) CPU mode register (CPUM) (Note 3) (44) Interrupt request register 1 (IREQ1) (45) Interrupt request register 2 (IREQ2) (46) Interrupt control register 1 (ICON1) (47) Interrupt control register 2 (ICON2) (48) Processor status register (49) Program counter (50) Watchdog timer H (51) Watchdog timer L 003916 003A16 003B16 003C16 003D16 003E16 003F16 (PS) (PCH) (PCL) 0016 0 0 1 1 1 1 1 1 0016 1 0 0 0 0 0 0 0 0016 0016 0016 0016 X X X X X 1 X X Contents of address FFFD16 Contents of address FFFC16 FF16 FF16 Notes 1: X : Undefined 2: The content of other registers is undefined when the microcomputer is reset. The initial values must be surely set before you use it. 3: When the setting by the function set ROM data 2 (FSROM2) is performed, the initial values of these registers at reset are changed. Fig. 66 Internal status of microcomputer at reset Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 54 of 89 7547 Group Clock Generating Circuit An oscillation circuit can be formed by connecting a resonator between XIN and XOUT, and an RC oscillation circuit can be formed by connecting a resistor and a capacitor. Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. (An external feed-back resistor may be needed depending on conditions.) (1) On-chip oscillator operation When the MCU operates by the on-chip oscillator for the main clock, connect XIN pin to VCC through a resistor and leave XOUT pin open. The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. (2) Ceramic resonator When the ceramic resonator is used for the main clock, connect the ceramic resonator and the external circuit to pins XIN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT. (3) RC oscillation When the RC oscillation is used for the main clock, connect the XIN pin and XOUT pin to the external circuit of resistor R and the capacitor C at the shortest distance. The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. (4) External clock When the external signal clock is used for the main clock, connect the XIN pin to the clock source and leave XOUT pin open. Select "0" (ceramic oscillation) to oscillation mode selection bit of CPU mode register (003B16). M37547 XIN R Note: The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. XOUT Be careful that variable frequencies and obtain Open the sufficient margin. Fig. 67 Processing of XIN and XOUT pins at on-chip oscillator operation M37547 XIN XOUT Rd CIN COUT Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between XIN and XOUT following the instruction. Fig. 68 External circuit of ceramic resonator Note: Connect the external M37547 XIN XOUT circuit of resistor R and the capacitor C at the shortest distance. The frequency is affected by a capacitor, R a resistor and a microcomputer. C So, set the constants within the range of the frequency limits. Fig. 69 External circuit of RC oscillation M37547 XIN XOUT Open External oscillation circuit VCC VSS Fig. 70 External clock input circuit Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 55 of 89 7547 Group (1) Oscillation control * Stop mode When the STP instruction is executed, the internal clock stops at an "H" level and the XIN oscillator stops. At this time, timer 1 is set to "0116" and prescaler 1 is set to "FF16" when the oscillation stabilization time set bit after release of the STP instruction is "0". On the other hand, timer 1 and prescaler 1 are not set when the above bit is "1". Accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. f(XIN)/16 is forcibly connected to the input of prescaler 1. When an external interrupt is accepted, oscillation is restarted but the internal clock remains at "H" until timer 1 underflows. As soon as timer 1 underflows, the internal clock is supplied. This is because when a ceramic oscillator is used, some time is required until a start of oscillation. In case oscillation is restarted by reset, no wait time is generated. So apply an "L" level to the RESET pin while oscillation becomes stable, or set the wait time by on-chip oscillator operation after system is released from reset until the oscillation is stabled. * Wait mode If the WIT instruction is executed, the internal clock stops at an "H" level, but the oscillator does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to "1" before the STP or WIT instruction is executed. s Notes on Clock Generating Circuit For use with the oscillation stabilization set bit after release of the STP instruction set to "1", set values in timer 1 and prescaler 1 after fully appreciating the oscillation stabilization time of the oscillator to be used. * Switch of ceramic and RC oscillations After releasing reset the operation starts by starting an on-chip oscillator. Then, a ceramic oscillation or an RC oscillation is selected by setting bit 5 of the CPU mode register. * Double-speed mode When a ceramic oscillation is selected, a double-speed mode can be used. Do not use it when an RC oscillation is selected. * CPU mode register Bits 5, 1 and 0 of CPU mode register are used to select oscillation mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing reset. After rewriting it is disable to write any data to the bit. (The emulator MCU "M37542RSS" is excluded.) Also, when the read-modify-write instructions (SEB, CLB) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. b7 b0 CPU mode register (Note 1) (CPUM: address 003B16, initial value: 8016) Processor mode bits b1 b0 0 0 Single-chip mode 0 1 Not available 1 0 Not available 1 1 Not available Stack page selection bit 0 : 0 page 1 : 1 page On-chip oscillator oscillation control bit (Note 3) 0 : On-chip oscillator oscillation enabled 1 : On-chip oscillator oscillation stop XIN oscillation control bit 0 : Ceramic or RC oscillation enabled 1 : Ceramic or RC oscillation stop Control by Function set ROM data 2 (FSROM2: address FFDA16) (Note 2) This cannot be controlled by FSROM2. This cannot be controlled by FSROM2. This bit function can be set by setting bit 4 of FSROM2. (Note 3) Bit 4 of FSROM2 = 0: Bit 3 of CPUM is fixed to "0". Bit 4 of FSROM2 = 1: Bit 3 of CPUM is "0" or "1". This cannot be controlled by FSROM2. This bit function can be set by setting bit 5 of FSROM2. (Note 4) Oscillation mode selection bit (Note 1, Note 4) Bit 5 of FSROM2 = 0: Bit 5 of CPUM is fixed to "0". 0 : Ceramic oscillation Bit 5 of FSROM2 = 1: Bit 5 of CPUM is "0" or "1". 1 : RC oscillation Clock division ratio selection bits This cannot be controlled by FSROM2. b7 b6 0 0 : f() = f(XIN)/2 (High-speed mode) 0 1 : f() = f(XIN)/8 (Middle-speed mode) 1 0 : applied from on-chip oscillator 1 1 : f() = f(XIN)/1 (Double-speed mode)(Note 5) Note 1: When the setting by the function set ROM data 2 (FSROM2) is performed, the initial value of CPUM is changed after releasing reset since bit 5 of CPUM is fixed. 2: The setting values of FSROM2 become valid by setting "0" to bit 0 of function set ROM data 0 (FSROM0). The setting values of FSROM2 are invalid by setting "1" to this bit. (In order that FSROM2 is invalid, write to CPUM after releasing reset.) 3: When bit 4 of FSROM2 is set to "0", the operation of on-chip oscillator cannot be stopped. Since the on-chip oscillator is not stopped also in the stop mode, the dissipation current in the stop mode is increased. 4: The setting value of bit 5 of CPUM can be fixed after releasing reset by setting value of bit 5 of FSROM2. Also, when the setting of FSROM2 is invalid, this bit can be rewritten only once after releasing reset. After rewriting it is disable to write any data to this bit. This bit is initialized by reset, and then, rewriting it is enabled. 5: This setting can be used only at ceramic oscillation. Do not use this at RC oscillation. Fig. 71 Structure of CPU mode register Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 56 of 89 7547 Group * Clock division ratio, XIN oscillation control, on-chip oscillator control The state transition shown in Fig. 75 can be performed by setting the clock division ratio selection bits (bits 7 and 6), XIN oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of CPU mode register. Be careful of notes on use in Fig. 75. * Count source (Timer 1, Timer A, Timer B, Timer X, Serial I/O, Serial I/O2, A/D converter, Watchdog timer) The count sources of these functions are affected by the clock division selection bit of the CPU mode register. The f(XIN) clock is supplied to the watchdog timer when selecting f(XIN) as the CPU clock. The on-chip oscillator output is supplied to these functions when selecting the on-chip oscillator output as the CPU clock. However, the watchdog timer is also affected by the function set ROM. q On-chip oscillation division ratio At on-chip oscillator mode, division ratio of on-chip oscillator for CPU clock is selected by setting value of on-chip oscillation division ratio selection register. The division ratio of on-chip oscillation for CPU clock is selected from among 1/1, 1/2, 1/8, 1/128. The operation clock for the peripheral function block is not changed by setting value of this register. s Notes on On-chip Oscillation Division Ratio * When system is released from reset, ROSC/8 (on-chip oscillator middle-speed mode) is selected for CPU clock. * When state transition from the ceramic or RC oscillation to onchip oscillator, ROSC/8 (on-chip oscillator middle-speed mode) is selected for CPU clock. * When the MCU operates by on-chip oscillator for the main clock without external oscillation circuit, connect XIN pin to VCC through a resistor and leave XOUT pin open. Set "10010x002" (x = 0 or 1) to CPUM. b7 b0 On-chip oscillation division ratio selection register (RODR: address 003716, initial value: 0216) On-chip oscillator division ratio b1 b0 0 0: On-chip oscillator double-speed mode (ROSC/1) 0 1: On-chip oscillator high-speed mode (ROSC/2) 1 0: On-chip oscillator middle-speed mode (ROSC/8) 1 1: On-chip oscillator low-speed mode (ROSC/128) Not used (returns "0" when read) Fig. 72 Structure of on-chip oscillation division ratio selection register Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 57 of 89 7547 Group XIN (Note) XOUT Clock division ratio selection bits Middle-, high-, double-speed mode 1/2 On-chip oscillator mode 1/4 1/2 Prescaler 1 Timer 1 Clock division ratio selection bits Middle-speed mode High-speed mode Double-speed mode On-chip oscillator Timing (Internal clock) 1/2 1/4 1/16 ROSC/128 ROSC/8 ROSC/2 ROSC/1 On-chip oscillator division ratio selection bits On-chip oscillator mode QS R STP instruction WIT instruction S R Q Q S RESET R STP instruction Reset Interrupt disable flag l Interrupt request Note: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. Fig. 73 Block diagram of internal clock generating circuit (for ceramic resonator) XOUT XIN Clock division ratio selection bits Middle-, high-, double-speed mode 1/2 On-chip oscillator mode 1/4 1/2 Prescaler 1 Timer 1 Delay Clock division ratio selection bits Middle-speed mode High-speed mode RING On-chip oscillator Double-speed mode Timing (Internal clock) 1/2 1/4 1/16 On-chip oscillator division ROSC/128 ratio selection bits ROSC/8 ROSC/2 ROSC/1 On-chip oscillator mode QS R STP instruction Reset Interrupt disable flag l Interrupt request WIT instruction S R Q Q S RESET R STP instruction Fig. 74 Block diagram of internal clock generating circuit (for RC oscillation) Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 58 of 89 7547 Group STP mode f(XIN) oscillation: stop On-chip oscillator: stop Interrupt STP instruction Interrupt STP instruction Interrupt STP instruction f(XIN) oscillation: enabled On-chip oscillator: stop f(XIN) oscillation: enabled On-chip oscillator: enabled Interrupt STP instruction f(XIN) oscillation: enabled On-chip oscillator: enabled f(XIN) oscillation: stop On-chip oscillator: enabled WAIT mode 1 Interrupt WIT instruction WAIT mode 2 Interrupt WIT instruction WAIT mode 3 Interrupt WIT instruction WAIT mode 4 Interrupt WIT instruction CPUM3=02 CPUM76=102 (Note 3) CPUM4=02 State 1 CPUM3=12 State 2 CPUM76=002 012 112 (Note 4) MISRG1=12 MISRG1=02 CPUM76=102 (Note 3) State 3 CPUM4=12 State 4 MISRG1=12 (Note 4) MISRG1=02 Reset released (Note 3) State 2' WIT instruction Interrupt CPUM76=002 012 112 State 3' WIT instruction Interrupt RESET state f(XIN) oscillation: enabled On-chip oscillator: enabled WAIT mode 2' f(XIN) oscillation: enabled On-chip oscillator: enabled Oscillation stop detection circuit valid WAIT mode 3' f(XIN) oscillation: enabled On-chip oscillator: enabled Operation clock source: f(XIN) (Note 1) Notes on switch of clock Operation clock source: On-chip oscillator (Note 2) (1) In operation clock = f(XIN), the following can be selected for the CPU clock division ratio. f(XIN)/2 (high-speed mode) f(XIN)/8 (middle-speed mode) f(XIN) (double-speed mode, only at a ceramic oscillation) (2) In operation clock = On-chip oscillator, the following can be selected for the CPU clock division ratio. ROSC/1 (On-chip oscillator double-speed mode) ROSC/2 (On-chip oscillator high-speed mode) ROSC/8 (On-chip oscillator middle-speed mode) ROSC/128 (On-chip oscillator low-speed mode) (3) After system is released from reset, and state transition of state 2 state 3 and state transition of state 2' state 3', ROSC/8 (On-chip oscillator middle-speed mode) is selected for CPU clock. (4) Executing the state transition state 3 to 2 or state 3' to 2' after stabilizing XIN oscillation. (5) When the state 2 state 3 state 4 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock. 1. CPUM76 = 102 (state 2 state 3) 2. NOP instruction Transition from Double-speed mode: NOP 3 Transition from High-speed mode: NOP 1 Transition from Middle-speed mode: NOP 0 3. CPU4 = 12 (state 3 state 4) (6) When the state 3 state 2 state 1 is performed, execute the NOP instruction as shown below according to the division ratio of CPU clock. 1. CPUM76 = 002 or 012 or 112 (state 3 state 2) 2. NOP instruction Transition from On-chip oscillator double-speed mode: NOP 4 Transition from On-chip oscillator high-speed mode: NOP 2 Transition from On-chip oscillator middle-speed mode: NOP 0 Transition from On-chip oscillator low-speed mode: NOP 0 3. CPUM3 = 12 (state 2 state 1) Fig. 75 State transition Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 59 of 89 7547 Group q Oscillation stop detection circuit The oscillation stop detection circuit is used for reset occurrence when a ceramic resonator or RC oscillation circuit stops by disconnection. To use this circuit, set an on-chip oscillator to be in active. The oscillation stop detection circuit is in active to set "1" to the ceramic or RC oscillation stop detection function active bit. When the oscillation stop detection circuit is in active, ceramic or RC oscillation is watched by the on-chip oscillator. When stop of ceramic or RC oscillation is detected, the oscillation stop detection status bit is set to "1". While "1" is set to the oscillation stop reset bit, internal reset occurs when oscillation stop is detected. The external reset and the oscillation stop reset can be discriminated by reading the oscillation stop detection status bit. The oscillation stop detection status bit retains "1", not initialized, when the oscillation stop reset occurs. The oscillation stop detection status bit is initialized to "0" when the external reset occurs. Accordingly, reset by oscillation stop can be confirmed by using this flag. s Notes on Oscillation Stop Detection Circuit * Do not execute the transition to "state 2'a" shown in Figure 77 because in this "state 2'a", MCU is stopped without reset even when XIN oscillation is stopped. * Ceramic or RC oscillation stop detection function active bit is not cleared by the oscillation stop internal reset. Accordingly, the oscillation stop detection circuit is in active when system is released from internal reset cause of oscillation stop detection. * Oscillation stop detection status bit is initialized by the following operation. (1) External reset (2) Write "0" data to the ceramic or RC oscillation stop detection function active bit. * The oscillation stop detection circuit is not included in the emulator MCU "M37542RSS". b7 b0 MISRG(address 003816, initial value: 0016) Oscillation stabilization time set bit after release of the STP instruction 0: Set "0116" in timer1, and "FF16" in prescaler 1 automatically 1: Not set automatically Ceramic or RC oscillation stop detection function active bit 0: Detection function inactive 1: Detection function active Oscillation stop reset bit 0: Oscillation stop reset disabled 1: Oscillation stop reset enabled Oscillation stop detection status bit 0: Oscillation stop not detected 1: Oscillation stop detected Not used (return "0" when read) Reserved bits (Do not write "1" to these bits) Fig. 76 Structure of MISRG Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 60 of 89 7547 Group CPUM76=102 (Note 4) State 2 f(XIN) oscillation: enabled On-chip oscillator: enabled CPUM76=002 012 112 (Note 3) State 3 f(XIN) oscillation: enabled On-chip oscillator: enabled MISRG1=02 (MISRG3 is cleared to "0".) Reset released (Note 4) RESET state 1 f(XIN) oscillation: enabled On-chip oscillator: enabled Applied "L" to RESET pin (external reset) MISRG3 is cleared to "0". MISRG1=12 MISRG1=02 (MISRG3 is cleared to "0".) MISRG1=12 (Note 3) State 2' f(XIN) oscillation: enabled On-chip oscillator: enabled State 3' f(XIN) oscillation: enabled On-chip oscillator: enabled State 2'a (Note 5) Oscillation stop reset disabled When oscillation stop is detected; MISRG3 is set to "1". Internal RESET does not occur. CPUM76=102 State 3'a Oscillation stop reset disabled When oscillation stop is detected; MISRG3 is set to "1". Internal RESET does not occur. Prohibitive state MUC will be locked when Ceramic or RC oscillation is stopped. CPUM76=002 012 112 State 3'c Release from internal reset MISRG3 is set to "1". Oscillation status can be confirmed by reading MISRG3. Reset released (Note 4) RESET state 2 f(XIN) oscillation: enabled On-chip oscillator: enabled MISRG2=12 MISRG2=02 MISRG2=12 MISRG2=02 State 2'b Oscillation stop reset enabled When oscillation stop is detected; MISRG3 is set to "1". Internal RESET occurs. CPUM76=102 (Note 4) State 3'b Oscillation stop reset enabled When oscillation stop is detected; MISRG3 is set to "1". Internal RESET occurs. CPUM76=002 012 112 Oscillation stop is detected (internal reset) Oscillation stop detection circuit is in active. (Note 6) Operation clock source: f(XIN) (Note 1) Notes on switch of clock Operation clock source: On-chip oscillator (Note 2) (1) In operation clock = f(XIN), the following can be selected for the CPU clock division ratio. f(XIN)/2 (High-speed mode) f(XIN)/8 (Middle-speed mode) f(XIN) (Double-speed mode, only at a ceramic oscillation) (2) In operation clock = On-chip oscillator, the following can be selected for the CPU clock division ratio. ROSC/1 (On-chip oscillator double-speed mode) ROSC/2 (On-chip oscillator high-speed mode) ROSC/8 (On-chip oscillator middle-speed mode) ROSC/128 (On-chip oscillator low-speed mode) (3) Executing the state transition state 3 to 2 or state 3 to 3' after stabilizing XIN oscillation. (4) After system is released from reset, and state transition of state 2 state 3 and state transition of state 2' state 3', ROSC/8 (On-chip oscillator middle-speed mode) is selected for CPU clock. (5) MCU cannot be returned by On-chip oscillator and its operation is stopped since internal reset does not occur at oscillation stop detected. Accordingly, do not execute the transition to state 2'a. (6) STP instruction cannot be used when oscillation stop detection circuit is in active. Fig. 77 State transition 2 Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 61 of 89 7547 Group q Function set ROM Figure 78 shows the Assignment of Function set ROM area. The random data are written to the Renesas shipment test areas (addresses FFD416 to address FFD716). Do not rewrite the data of these areas. When the checksum is included in the user program, avoid assigning it to these areas. The function set ROM data 0 to 2 (addresses FFD816 to FFDA16) are used to set the peripheral function. Data set to these areas become valid after releasing reset. The ROM code protect to disable the reading of the built-in QzROM area is assigned to address FFDB16. [Function set ROM data] FSROM0, FSROM1, FSROM2 Function set ROM data 0 to 2 (addresses FFD816 to FFDA16) are used to set modes of peripheral functions. By setting values to these areas, the operation mode of each peripheral function are set after releasing reset. Refer to the descriptions of peripheral functions for the details of operation of peripheral functions. - CPU mode register - Watchdog timer - Low voltage detection circuit When "1" is set to bit 0 of function set ROM data 0 (address FFD816), the written values to bit 5 to bit 0 of function set ROM data 2 (address FFDA16) can become invalid. When the values of bit 5 to bit 0 of function set ROM data 2 (address FFDA16) are invalid, the operation mode of the peripheral functions can be set by setting the related registers. [ROM code protect] By setting "0016" to ROM code protect (address FFDB16), reading of the built-in QzROM by the serial programmer is disabled. b7 b0 10 00 0 Function set ROM data 0 (FSROM0: address FFD816) Function set ROM invalid bit (Note 1) 0: Setting of bit 5 to bit 0 of function set ROM data 2 valid 1: Setting of bit 5 to bit 0 of function set ROM data 2 invalid Low voltage detection circuit valid bit 0: Low voltage detection circuit invalid 1: Low voltage detection circuit valid Set "0" to this bit certainly. Low voltage detection circuit valid bit in the stop mode (Note 2) 0: Low voltage detection circuit invalid in the stop mode 1: Low voltage detection circuit valid in the stop mode Set "0" to these bits. Set "1" to this bit. Note 1: When "1" is set to this bit, the setting values of bit 5 to bit 0 of function set ROM data 2 become invalid, and these functions can be set by program. (this bit does not affect on other bits than bit 5 to bit 0 of function set ROM data 2.) 2: When the Low voltage detection circuit is set to be valid in the stop mode, the dissipation current in the stop mode is increased. Fig. 79 Structure of Function set ROM data 0 b7 b0 00000000 Function set ROM data 1 FSROM1 (FFD916) Set "0" to these bits certainly. Fig. 80 Structure of Function set ROM data 1 b7 b0 00 Function set ROM data 2 (FSROM2: address FFDA16) Watchdog timer source clock selection bit (Note 1) 0 : On-chip oscillator/16 1 : On-chip oscillator/16 or f(XIN)/16 Watchdog timer start selection bit (Note 1) 0 : Watchdog timer starts automatically after reset 1 : Watchdog timer is inactive after reset Watchdog timer H count source selection bit (Note 1) 0 :Watchdog timer L underflow 1 : Count source of watchdog timer L (The clock selected by the watchdog timer source clock selection bit (bit 0)) STP instruction function selection bit (Note 1) 0 : System enters into the stop mode at the STP instruction execution 1 : Internal reset occurs at the STP instruction execution On-chip oscillator control bit (Note 1) 0 : Stop of on-chip oscillator disabled 1 : Stop of on-chip oscillator enabled Oscillation mode selection bit (Note 1) 0 : Ceramic oscillation 1 : RC oscillation Addres FFD416 Renesas shipment test area FFD516 Renesas shipment test area FFD616 Renesas shipment test area FFD716 Renesas shipment test area FFD816 Function set ROM data 0 FFD916 Function set ROM data 1 FFDA16 Function set ROM data 2 FFDB16 ROM code protect Interrupt vector area Note: The random data are written into the Renesas shipment test areas (address FFD416 to address FFD716). Do not rewrite the data of these areas. When checksum is included in user program, avoid assigning it to these areas. Fig. 78 Assignment of Function set ROM area Set "0" to these bits certainly. Note 1: These functions can be active when "0" is set to function set ROM valid bit (bit 0 of function set ROM data 0). Fig. 81 Structure of Function set ROM data 2 Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 62 of 89 7547 Group NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after reset are undefined except for the interrupt disable flag I which is "1". After reset, initialize flags which affect program execution. In particular, it is essential to initialize the T flag and the D flag because of their effect on calculations. State transition Do not stop the clock selected as the operation clock because of setting of CM3, 4. NOTES ON HARDWARE Handling of Power Source Pin In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F to 0.1 F is recommended. Interrupts The contents of the interrupt request bit do not change even if the BBC or BBS instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruction before executing the BBC or BBS instruction. Decimal Calculations * For calculations in decimal notation, set the decimal mode flag D to "1", then execute the ADC instruction or SBC instruction. In this case, execute SEC instruction, CLC instruction or CLD instruction after executing one instruction before the ADC instruction or SBC instruction. * In the decimal mode, the values of the N (negative), V (overflow) and Z (zero) flags are invalid. Ports * The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is "1", addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read/modify/write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA instruction, etc. A/D Conversion Do not execute the STP instruction during A/D conversion. Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock by the number of cycles mentioned in the machine-language instruction table. The frequency of the internal clock is the same as that of the XIN in double-speed mode, twice the XIN cycle in high-speed mode and 8 times the XIN cycle in middle-speed mode. CPU Mode Register The oscillation mode selection bit and processor mode bits can be rewritten only once after releasing reset. However, after rewriting it is disable to write any value to the bit. (Emulator MCU is excluded.) When a ceramic oscillation is selected, a double-speed mode of the clock division ratio selection bits can be used. Do not use it when an RC oscillation is selected. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 63 of 89 7547 Group NOTES ON USE Countermeasures against noise 1. Shortest wiring length (1) Package Select the smallest possible package to make the total wiring length short. (3) Wiring for clock input/output pins * Make the length of wiring which is connected to clock I/O pins as short as possible. * Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. * Separate the VSS pattern only for oscillation from other VSS patterns. DIP SDIP SOP QFP Noise XIN XOUT VSS N.G. Fig. 84 Wiring for clock I/O pins XIN XOUT VSS O.K. Fig. 82 Selection of packages (2) Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). Noise Reset circuit VSS N.G. RESET VSS (4) Wiring to VPP pin Connect VPP pin to a GND pattern at the shortest distance. The GND pattern is required to be as close as possible to the GND supplied to VSS. In order to improve the noise reduction, to connect a 5 k resistor serially to the VPP pin - GND line may be valid. As well as the above-mentioned, in this case, connect to a GND pattern at the shortest distance. The GND pattern is required to be as close as possible to the GND supplied to VSS. (Note) The shortest CNVSS/VPP About 5k Reset circuit VSS RESET VSS VSS (Note) The shortest Note: This indicates pin. O.K. Fig. 83 Wiring for the RESET pin Fig. 85 Wiring for the VPP pin of the QzPROM Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 64 of 89 7547 Group 2. Connection of bypass capacitor across VSS line and VCC line Connect an approximately 0.1 F bypass capacitor across the VSS line and the VCC line as follows: * Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. * Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. * Use lines with a larger diameter than other signal lines for VSS line and VCC line. * Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. VCC VCC 3. Wiring to analog input pins * Connect an approximately 100 to 1 k resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. * Connect an approximately 1000 pF capacitor across the Vss pin and the analog input pin. Besides, connect the capacitor to the Vss pin as close as possible. Also, connect the capacitor across the analog input pin and the Vss pin at equal length. VSS VSS Noise (Note) N.G. O.K. Microcomputer Analog input pin N.G. O.K. Fig. 86 Bypass capacitor across the VSS line and the VCC line Thermistor VSS Note : The resistor is used for dividing resistance with a thermistor. Fig. 87 Analog signal line and a resistor and a capacitor * The analog input pin is connected to the capacitor of a voltage comparator. Accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of A/D conversion when the analog signal source of high-impedance is connected to an analog input pin. In order to obtain the A/D conversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 65 of 89 7547 Group 4. Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. (3) Oscillator protection using Vss pattern As for a two-sided printed circuit board, print a Vss pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the Vss pattern to the microcomputer Vss pin with the shortest possible wiring. Besides, separate this Vss pattern from other Vss patterns. An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example XIN XOUT VSS Separate the VSS line for oscillation from other VSS lines Fig. 89 Vss pattern on the underside of an oscillator Keeping oscillator away from large current signal lines Microcomputer Mutual inductance M Large current GND Installing oscillator away from signal lines where potential levels change frequently XIN XOUT VSS N.G. Do not cross CNTR XIN XOUT VSS Fig. 88 Wiring for a large current signal line/Writing of signal lines where potential levels change frequently Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 66 of 89 7547 Group 5. Setup for I/O ports Setup I/O ports using hardware and software as follows: O.K. Noise Data bus Direction register N.G. Port latch I/O port pins Noise Fig. 90 Setup for I/O ports 6. Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. Main routine (SWDT) N CLI Main processing N (SWDT) =N? N Interrupt processing routine (SWDT) (SWDT)--1 Interrupt processing (SWDT) 0? 0 >0 RTI Return Main routine errors Interrupt processing routine errors Fig. 91 Watchdog timer by software Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 67 of 89 7547 Group ELECTRICAL CHARACTERISTICS of 7547 Group Absolute Maximum Ratings Absolute maximum ratings Symbol VCC VI VI VI VO Pd Topr Tstg Parameter Power source voltage Input voltage P00-P07, P10-P14, P20-P27, P30-P37, VREF Input voltage RESET, XIN Input voltage CNVSS Output voltage P00-P07, P10-P14, P20-P27, P30-P37, XOUT Power dissipation Operating temperature Storage temperature Conditions All voltages are based on VSS. When an input voltage is measured, output transistors are cut off. Ta = 25C Ratings -0.3 to 6.5 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 300 -20 to 85 -40 to 125 Unit V V V V V mW C C Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 68 of 89 7547 Group Recommended Operating Conditions Recommended operating conditions (1) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VCC Parameter Power source voltage (Double-speed mode) (ceramic) Limits Min. 4.5 4.0 2.4 2.2 4.0 2.4 2.2 4.0 2.4 2.2 1.8 1.8 0.8VCC 2.0 0.8VCC 0 0 0 0 Typ. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 VCC VCC VCC VCC 0.2VCC 0.8 0.2VCC 0.16VCC -80 80 80 -40 40 40 Unit V V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA f(XIN) = 8 MHz f(XIN) = 6.5 MHz f(XIN) = 2 MHz f(XIN) = 1 MHz (High-, Middle-speed mode) f(XIN) = 8 MHz f(XIN) = 4 MHz f(XIN) = 2 MHz Power source voltage (High-, Middle-speed mode) f(XIN) = 4 MHz (RC) f(XIN) = 2 MHz f(XIN) = 1 MHz Power source voltage (at on-chip oscillator) VSS Power source voltage VREF Analog reference voltage VIH "H" input voltage P00-P07, P10-P14, P20-P27, P30-P37 VIH "H" input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) VIH "H" input voltage RESET, XIN VIL "L" input voltage P00-P07, P10-P14, P20-P27, P30-P37 VIL "L" input voltage (TTL input level selected) P10, P12, P13, P36, P37 (Note 1) VIL "L" input voltage RESET, CNVSS VIL "L" input voltage XIN IOH(peak) "H" total peak output current (Note 2) P00-P07, P10-P14, P20-P27, P30-P37 IOL(peak) "L" total peak output current (Note 2) P10-P14, P20-P27 IOL(peak) "L" total peak output current (Note 2) P00-P07, P30-P37 IOH(avg) "H" total average output current (Note 2) P00-P07, P10-P14, P20-P27, P30-P37 IOL(avg) "L" total average output current (Note 2) P10-P14, P20-P27 IOL(avg) "L" total average output current (Note 2) P00-P07, P30-P37 Note 1: Vcc = 4.0 to 5.5V 2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 69 of 89 7547 Group Recommended operating conditions (2) (VCC = 1.8 to 5.5V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) f(XIN) "H" peak output current (Note 1) "L" peak output current (Note 1) "L" peak output current (Note 1) "H" average output current (Note 2) "L" average output current (Note 2) Parameter P00-P07, P10-P14, P20-P27, P30-P37 P00-P07, P30-P37 (Drive capacity = "L") P10-P14, P20-P27 P00-P07, P30-P37 (Drive capacity = "H") P00-P07, P10-P14, P20-P27, P30-P37 P00-P07, P30-P37 (Drive capacity = "L") P10-P14, P20-P27 P00-P07, P30-P37 (Drive capacity = "H") Min. Typ. Max. -10 10 30 -5 5 15 8 Unit mA mA mA mA mA mA MHz "L" average output current (Note 2) Oscillation frequency (Note 3) at ceramic oscillation or external clock input (VCC = 4.5 V to 5.5 V) Double-speed mode Oscillation frequency (Note 3) at ceramic oscillation or external clock input (VCC = 4.0 V to 5.5 V) Double-speed mode Oscillation frequency (Note 3) at ceramic oscillation or external clock input (VCC = 2.4 V to 5.5 V) Double-speed mode Oscillation frequency (Note 3) at ceramic oscillation or external clock input (VCC = 2.2 V to 5.5 V) Double-speed mode Oscillation frequency (Note 3) at ceramic oscillation or external clock input (VCC = 4.0 V to 5.5 V) High-, Middle-speed mode Oscillation frequency (Note 3) at ceramic oscillation or external clock input (VCC = 2.4 V to 5.5 V) High-, Middle-speed mode Oscillation frequency (Note 3) at ceramic oscillation or external clock input (VCC = 2.2 V to 5.5 V) High-, Middle-speed mode Oscillation frequency (Note 3) at RC oscillation (VCC = 4.0 V to 5.5 V) High-, Middle-speed mode Oscillation frequency (Note 3) at RC oscillation (VCC = 2.4 V to 5.5 V) High-, Middle-speed mode Oscillation frequency (Note 3) at RC oscillation (VCC = 2.2 V to 5.5 V) High-, Middle-speed mode 6.5 MHz 2 MHz 1 MHz 8 MHz 4 MHz 2 MHz 4 MHz 2 MHz 1 MHz Notes 1: The peak output current is the peak current flowing in each port. 2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 3: When the oscillation frequency has a duty cycle of 50 %. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 70 of 89 7547 Group Electrical Characteristics Electrical characteristics (1) (VCC = 1.8 to 5.5V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol VOH Parameter "H" output voltage P00-P07, P10-P14, P20-P27, P30-P37 (Note 1) Test conditions IOH = -5 mA VCC = 4.0 to 5.5 V IOH = -1.0 mA VCC = 1.8 to 5.5 V IOL = 5 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 1.8 to 5.5 V IOL = 15 mA VCC = 4.0 to 5.5 V IOL = 1.5 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 1.8 to 5.5 V Min. VCC-1.5 VCC-1.0 1.5 0.3 1.0 2.0 0.3 1.0 0.4 Typ. Max. Unit V V V V V V V V V VOL "L" output voltage P00-P07, P30-P37 (Drive capacity = "L") P10-P14, P20-P27 VOL "L" output voltage P00-P07, P30-P37 (Drive capacity = "H") VT+-VT- Hysteresis CNTR0, INT0, INT1, CAP0, CAP1 (Note 2) P00-P07 (Note 3) VT+-VT- Hysteresis RXD0, SCLK0, RXD1, SCLK1 VT+-VT- Hysteresis RESET IIH "H" input current P00-P07, P10-P14, P20-P27, P30-P37 IIH IIH IIL "H" input current RESET "H" input current XIN "L" input current P00-P07, P10-P14, P20-P27, P30-P37 "L" input current RESET "L" input current XIN "L" input current P00-P07, P30-P37 RAM hold voltage On-chip oscillator oscillation frequency Oscillation stop detection circuit detection frequency 0.5 0.5 VI = VCC (Pin floating. Pull up transistors "off") VI = VCC VI = VCC VI = VSS (Pin floating. Pull up transistors "off") VI = VSS VI = VSS VI = VSS (Pull up transistors "on") When clock stopped VCC = 5.0 V, Ta = 25 C VCC = 5.0 V, Ta = 25 C -4.0 -0.2 1.6 1000 62.5 -0.5 5.5 3000 187.5 4.0 -5.0 5.0 V V A A A A A A mA V kHz kHz 5.0 IIL IIL IIL VRAM ROSC DOSC -5.0 2000 125 Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is "0". P05 is measured when the P05/TXD2 P-channel output disable bit of the UART2 control register (bit 4 of address 003116) is "0". 2: RXD1, SCLK1, INT0, and INT1 (P36 selected) have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to "0" (CMOS level). 3: It is available only when operating key-on wake up. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 71 of 89 7547 Group Electrical characteristics (2) (VCC = 1.8 to 5.5V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Limits Symbol ICC Parameter Power source f(XIN) = 8 MHz current Output transistors "off" *LVD is valid (except at STP) f(XIN) = 2 MHz, VCC = 2.2 V Output transistors "off" On-chip oscillator operation mode, Output transistors "off" Test conditions Double-speed mode High-speed mode Middle-speed mode High-speed mode Min. Typ. 5.9 3.9 2.4 0.45 Max. 9.5 7.0 5.5 1.25 Unit mA mA mA mA Frequency/1 Frequency/2 Frequency/8 Frequency/128 f(XIN) = 8 MHz (in WIT state), functions except timer 1 disabled, Output transistors "off" f(XIN) = 2 MHz, VCC = 2.2 V (in WIT state), functions except timer 1 disabled, Output transistors "off" On-chip oscillator operation mode, (in WIT state), functions except timer 1 disabled, Output transistors "off" Increment when A/D conversion is executed f(XIN) = 8 MHz, VCC = 5 V Ta = 25 C All oscillation stopped Ta = 85 C (in STP state) Output transistors "off" Low voltage detection circuit self consumption current Ta = 25 C VCC = 5 V 1.55 0.95 0.4 0.25 2.0 3.3 2.3 1.1 0.7 3.5 mA mA mA mA mA 0.25 mA 0.25 0.7 mA 0.5 0.1 1.0 10 mA A A A 70 Note: Increment when A/D conversion is executed includes the reference power source input current (IVREF). Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 72 of 89 7547 Group A/D Converter Characteristics A/D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol -- -- tCONV Parameter Resolution Absolute accuracy Conversion time Test conditions Limits Min. Typ. Max. 10 3 122 61 50 30 55 150 90 200 120 5.0 Unit Bits LSB tc(XIN) k A A Ta = 25 C VCC = VREF = 2.7 to 5.5 V AD conversion clock = f(XIN)/2 AD conversion clock = f(XIN) VREF = 5.0 V VREF = 3.0 V RLADDER Ladder resistor IVREF Reference power source input current II(AD) A/D port input current Note: AD conversion accuracy may be low under the following conditions; (1) When the VREF voltage is set to be lower than the VCC voltage, an analog circuit in this microcomputer is affected by noise. The accuracy is lower than the case the VREF voltage is the same as VCC voltage. (2) When the VREF voltage is 3.0 V or less at the low temperature, the AD conversion accuracy may be very lower than at room temperature. When system is used at low temperature, that VREF is 3.0 V or more is recommended. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 73 of 89 7547 Group Power-on reset circuit characteristics Power-on reset circuit characteristics (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VPOR TW(VPOR) TW(VPOR-VDET) Parameter Valid start voltage of power-on reset circuit (Note) VPOR hold time Rising time of valid power source of power-on reset circuit Test conditions Limits Min. Typ. Max. 0 10 20 Unit mV s ms TW(VPOR) > 10 s Note: VPOR is the start voltage level of Vcc for the built-in power-on reset circuit to operate normally. Keep VPOR to be lower than the Vcc voltage before rising of the Vcc power source to use the built-in power-on reset circuit. Set the built-in low voltage detection circuit to be valid when the built-in power-on reset is used. Low voltage detection circuit characteristics Low voltage detection circuit characteristics (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VLVD TW(VLVD) TW(VLVD-VDET) VDETParameter Valid start voltage of low voltage detection circuit (Note) VLVD hold time Test conditions Limits Min. 1.0 Typ. Max. 0 10 10 2.05 2.1 Unit V s s V V V s Rising time of valid power source of low voltage detection circuit TW(VLVD) > 10 s Detection voltage of low voltage detection circuit Ta = 0 to 50 C Ta = -20 to 85 C V(VDET+-VDET-) Detection voltage Hysteresis (when hysteresis is valid) Ta = -20 to 85 C TDET Detection time of low 5voltage detection circuit 1.85 1.8 1.95 1.95 0.1 20 Note: VLVD is the start voltage level of Vcc for the built-in low voltage detection circuit to operate normally. If the Vcc power source becomes lower than VLVD, first set the Vcc voltage to be lower than VPOR. Next, according to the electrical characteristics of the power-on reset circuit, perform the rising of Vcc. Vcc power source waveform VPOR 0V TW(VPOR) Internal reset signal VDET+ VDET- Note VPOR T(VPON-VDET) TDET TW(VLVD) T(VLVD-VDET) Power-on reset circuit characteristics Low voltage detection circuit characteristics Note: If the schmitt of the voltage drop detection circuit is set to be invalid, system is released from reset at the timing of rising to power source voltage VDET-. Fig. 92 Electrical characteristics of power-on reset circuit and voltage drop detection circuit Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 74 of 89 7547 Group Timing Requirements Table 22 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1-SCLK1) th(SCLK1-RxD1) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1, CAP0, CAP1 input "H" pulse width (Note 1) CNTR0, INT0, INT1, CAP0, CAP1 input "L" pulse width (Note 1) Serial I/O1, serial I/O2 clock input cycle time (Note 2) Serial I/O1, serial I/O2 clock input "H" pulse width (Note 2) Serial I/O1, serial I/O2 clock input "L" pulse width (Note 2) Serial I/O1, serial I/O2 input set up time Serial I/O1, serial I/O2 input hold time Min. 2 125 50 50 200 80 80 800 370 370 220 100 Limits Typ. Max. s ns ns ns ns ns ns ns ns ns ns ns Unit Notes 1: As for CAP0, CAP1, it is the value when noise filter is not used. 2: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to "1" (clock synchronous serial I/O is selected). When bit 6 of the serial I/O1 control register is "0" (clock asynchronous serial I/O is selected), the rating values are divided by 4. In this time, bit 6 of the serial I/O2 control register (address 003016) is set to "1" (clock synchronous serial I/O is selected). When bit 6 of the serial I/O2 control register is "0" (clock asynchronous serial I/O is selected), the rating values are divided by 4. Table 23 Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1-SCLK1) th(SCLK1-RxD1) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1, CAP0, CAP1 input "H" pulse width (Note 1) CNTR0, INT0, INT1, CAP0, CAP1 input "L" pulse width (Note 1) Serial I/O1, serial I/O2 clock input cycle time (Note 2) Serial I/O1, serial I/O2 clock input "H" pulse width (Note 2) Serial I/O1, serial I/O2 clock input "L" pulse width (Note 2) Serial I/O1, serial I/O2 input set up time Serial I/O1, serial I/O2 input hold time Min. 2 250 100 100 500 230 230 2000 950 950 400 200 Limits Typ. Max. s ns ns ns ns ns ns ns ns ns ns ns Unit Notes 1: As for CAP0, CAP1, it is the value when noise filter is not used. 2: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to "1" (clock synchronous serial I/O is selected). When bit 6 of the serial I/O1 control register is "0" (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. In this time, bit 6 of the serial I/O2 control register (address 003016) is set to "1" (clock synchronous serial I/O is selected). When bit 6 of the serial I/O2 control register is "0" (clock asynchronous serial I/O is selected), the rating values are divided by 4. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 75 of 89 7547 Group Table 24 Timing requirements (3) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR0) tWH(CNTR0) tWL(CNTR0) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RxD1-SCLK1) th(SCLK1-RxD1) Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0 input cycle time CNTR0, INT0, INT1, CAP0, CAP1 input "H" pulse width (Note 1) CNTR0, INT0, INT1, CAP0, CAP1 input "L" pulse width (Note 1) Serial I/O1, serial I/O2 clock input cycle time (Note 2) Serial I/O1, serial I/O2 clock input "H" pulse width (Note 2) Serial I/O1, serial I/O2 clock input "L" pulse width (Note 2) Serial I/O1, serial I/O2 input set up time Serial I/O1, serial I/O2 input hold time Min. 2 500 200 200 1000 460 460 4000 1900 1900 800 400 Limits Typ. Max. s ns ns ns ns ns ns ns ns ns ns ns Unit Notes 1: As for CAP0, CAP1, it is the value when noise filter is not used. 2: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to "1" (clock synchronous serial I/O is selected). When bit 6 of the serial I/O1 control register is "0" (clock asynchronous serial I/O1 is selected), the rating values are divided by 4. In this time, bit 6 of the serial I/O2 control register (address 003016) is set to "1" (clock synchronous serial I/O is selected). When bit 6 of the serial I/O2 control register is "0" (clock asynchronous serial I/O is selected), the rating values are divided by 4. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 76 of 89 7547 Group Switching Characteristics Table 25 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TxD1) tv(SCLK1-TxD1) tr(SCLK1) tf(SCLK1) tr(CMOS) tf(CMOS) Parameter Serial I/O1, serial I/O2 clock output "H" pulse width Serial I/O1, serial I/O2 clock output "L" pulse width Serial I/O1, serial I/O2 output delay time Serial I/O1, serial I/O2 output valid time Serial I/O1, serial I/O2 clock output rising time Serial I/O1, serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Limits Min. tC(SCLK1)/2-30 tC(SCLK1)/2-30 140 -30 30 30 30 30 Typ. Max. Unit ns ns ns ns ns ns ns ns 10 10 Note 1: Pin XOUT is excluded. Table 26 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TxD1) tv(SCLK1-TxD1) tr(SCLK1) tf(SCLK1) tr(CMOS) tf(CMOS) Parameter Serial I/O1, serial I/O2 clock output "H" pulse width Serial I/O1, serial I/O2 clock output "L" pulse width Serial I/O1, serial I/O2 output delay time Serial I/O1, serial I/O2 output valid time Serial I/O1, serial I/O2 clock output rising time Serial I/O1, serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Limits Min. tC(SCLK1)/2-50 tC(SCLK1)/2-50 350 -30 50 50 50 50 Typ. Max. Unit ns ns ns ns ns ns ns ns 20 20 Note 1: Pin XOUT is excluded. Table 27 Switching characteristics (3) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TxD1) tv(SCLK1-TxD1) tr(SCLK1) tf(SCLK1) tr(CMOS) tf(CMOS) Parameter Serial I/O1, serial I/O2 clock output "H" pulse width Serial I/O1, serial I/O2 clock output "L" pulse width Serial I/O1, serial I/O2 output delay time Serial I/O1, serial I/O2 output valid time Serial I/O1, serial I/O2 clock output rising time Serial I/O1, serial I/O2 clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) Limits Min. tC(SCLK1)/2-70 tC(SCLK1)/2-70 450 -30 70 70 70 70 Typ. Max. Unit ns ns ns ns ns ns ns ns 25 25 Note 1: Pin XOUT is excluded. Measured output pin 100 pF /// CMOS output Switching characteristics measurement circuit diagram Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 77 of 89 7547 Group tC(CNTR0) tWH(CNTR0) tWL(CNTR0) 0.2VCC CNTR0 0.8VCC tWH(INT0) tWL(INT0) 0.2VCC INT0, INT1 CAP0, CAP1 0.8VCC tW(RESET) RESET 0.2VCC 0.8 VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC tC(SCLK1) tf tWL(SCLK1) 0.2VCC tsu(RxD1-SCLK1) tr 0.8VCC tWH(SCLK1) SCLK1 th(SCLK1-RxD1) RXD1 (at receive) td(SCLK1-TxD1) 0.8VCC 0.2 VCC tv(SCLK1-TxD1) TXD1 (at transmit) Fig. 93 Timing chart Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 78 of 89 7547 Group PACKAGE OUTLINE JEITA Package Code P-SSOP36-8.4x15-0.80 RENESAS Code PRSP0036GA-B Previous Code 36P2R-D MASS[Typ.] 0.5g 36 19 HE *1 E F 1 Index mark 18 c NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. *2 D A2 *3 A1 Reference Symbol A Dimension in Millimeters e y bp D E A2 A A1 bp c HE e y L Detail F Min Nom Max 14.8 15.0 15.2 8.2 8.4 8.6 2.05 2.35 0 0.1 0.2 0.3 0.35 0.45 0.18 0.2 0.25 0 8 11.63 11.93 12.23 0.65 0.8 0.95 0.10 0.3 0.5 0.7 Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 79 of 89 L 7547 Group APPENDIX NOTES ON PROGRAMMING 1. Processor Status Register (1) Initializing of processor status register Flags which affect program execution must be initialized after a reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. (2) Notes on status flag in decimal mode When decimal mode is selected, the values of three of the flags in the status register (the N, V, and Z flags) are invalid after a ADC or SBC instruction is executed. The carry flag (C) is set to "1" if a carry is generated as a result of the calculation, or is cleared to "0" if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to "0" before each calculation. To check for a borrow, the C flag must be initialized to "1" before each calculation. Reset Initializing of flags Main program Set D flag to "1" ADC or SBC instruction NOP instruction SEC, CLC, or CLD instruction Fig. 4 Status flag at decimal calculations 3. JMP instruction When using the JMP instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. 4. Multiplication and Division Instructions (1) The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. (2) The execution of these instructions does not change the contents of the processor status register. 5. Read-modify-write instruction Do not execute a read-modify-write instruction to the read invalid address (SFR). The read-modify-write instruction operates in the following sequence: read one-byte of data from memory, modify the data, write the data back to original memory. The following instructions are classified as the read-modify-write instructions in the 740 Family. (1) Bit management instructions: CLB, SEB (2) Shift and rotate instructions: ASL, LSR, ROL, ROR, RRF (3) Add and subtract instructions: DEC, INC (4) Logical operation instructions (1's complement): COM Add and subtract/logical operation instructions (ADC, SBC, AND, EOR, and ORA) when T flag = "1" operate in the way as the readmodify-write instruction. Do not execute the read invalid SFR. Fig. 1 Initialization of processor status register (2) How to reference the processor status register To reference the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its original status. PLP instruction execution Fig. 2 Sequence of PLP instruction execution (S) (S)+1 Stored PS Fig. 3 Stack memory contents after PHP instruction execution 2. Decimal calculations (1) Execution of decimal calculations The ADC and SBC are the only instructions which will yield proper decimal notation, set the decimal mode flag (D) to "1" with the SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, or CLD instruction. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 80 of 89 7547 Group NOTES ON PERIPHERAL FUNCTIONS Notes on I/O Ports 1. Port P0P3 drive capacity control register The number of LED drive port (drive capacity is HIGH) is 8. 2. Pull-up control register When using each port which built in pull-up resistor as an output port, the pull-up control bit of corresponding port becomes invalid, and pull-up resistor is not connected. 4. Modifying output data with bit managing instruction When the port latch of an I/O port is modified with the bit managing instruction*2, the value of the unspecified bit may be changed. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 81 of 89 7547 Group 5. Direction register The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is "1", addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read-modify-write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA instruction, etc. Notes on Interrupts 1. Change of relevant register settings When not requiring for the interrupt occurrence synchronous with the following case, take the sequence shown in Figure 5. * When switching external interrupt active edge * When switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated Set the corresponding interrupt enable bit to "0" (disabled) . Set the interrupt edge selection bit, active edge switch bit, or the interrupt source selection bit. NOP (One or more instructions) Set the corresponding interrupt request bit to "0" (no interrupt request issued). Set the corresponding interrupt enable bit to "1" (enabled). Fig. 5 Sequence of changing relevant register Termination of Unused Pins 1. Terminate unused pins Perform the following wiring at the shortest possible distance (20 mm or less) from microcomputer pins. (1) I/O ports Set the I/O ports for the input mode and connect each pin to VCC or VSS through each resistor of 1 k to 10 k. The port which can select a built-in pull-up resistor can also use the built-in pull-up resistor. When using the I/O ports as the output mode, open them at "L" or "H". * When opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. Thus, the potential at these pins is undefined and the power source current may increase in the input mode. With regard to an effects on the system, thoroughly perform system evaluation on the user side. * Since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. 2. Termination remarks (1) I/O ports setting as input mode [1] Do not open in the input mode. Set the interrupt request bit to "0" (no interrupt issued) NOP (one or more instructions) Execute the BBC or BBS instruction Fig. 6 Sequence of check of interrupt request bit Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 82 of 89 7547 Group 3. Interrupt discrimination bit Use an LDM instruction to clear to "0" an interrupt discrimination bit. LDM #%0000XXXX, $0B Set the following values to "X" "0": an interrupt discrimination bit to clear "1": other interrupt discrimination bits Ex.) When a key-on wakeup interrupt discrimination bit is cleared; LDM #%00001110 and $0B. 4. Interrupt discrimination bit and interrupt request bit For key-on wakeup, UART1 bus collision detection, A/D conversion and Timer 1 interrupt, even if each interrupt valid bit (interrupt source set register (address 0A16)) is set "0: Invalid", each interrupt discrimination bit (interrupt source discrimination register (address 0B16)) is set to "1: interrupt occurs" when corresponding interrupt request occurs. But corresponding interrupt request bit (interrupt request registers 1, 2 (addresses 3C16, 3D16) is not affected. Notes on Timers 1. When n (0 to 255) is written to a timer latch, the frequency division ratio is 1/(n+1). 2. When a count source of timer X, timer A or timer B is switched, stop a count of the timer. Notes on Timer X 1. CNTR0 interrupt active edge selection CNTR0 interrupt active edge depends on the CNTR0 active edge switch bit (bit 2 of timer X mode register (address 2B16)). When this bit is "0", the CNTR0 interrupt request bit is set to "1" at the falling edge of CNTR0 pin input signal. When this bit is "1", the CNTR0 interrupt request bit is set to "1" at the rising edge of CNTR0 pin input signal. 2. Timer X count source selection The f(XIN) (frequency not divided) can be selected by the timer X count source selection bits (bits 1 and 0 of timer count source set register (address 2A16)) only when the ceramic oscillation or the on-chip oscillator is selected. Do not select it for the timer X count source at the RC oscillation. 3. Pulse output mode Set the direction register of port P14, which is also used as CNTR0 pin, to output. When the TXOUT pin is used, set the direction register of port P03, which is also used as TXOUT pin, to output. 4. Pulse width measurement mode Set the direction register of port P14, which is also used as CNTR0 pin, to input. Notes on Timer A, B 1. Setting of timer value When "1: Write to only latch" is set to the timer A (B) write control bit (bit 0 (bit 2) of timer X mode register (address 1D16)), written data to timer register is set to only latch even if timer is stopped or operating. Accordingly, in order to set the initial value for timer when it is stopped, set "0: Write to latch and timer simultaneously" to timer A (B) write control bit. 2. Read/write of timer A Stop timer A to read/write its data in the following state; XIN oscillation selected by clock division ratio selection bits (bits 7 and 6 of CPU mode register (address 3B16)), and the on-chip oscillator output is selected as the timer A count source. 3. Read/write of timer B Stop timer B to read/write its data in the following state; XIN oscillation selected by clock division ratio selection bits, the timer A underflow is selected as the timer B count source, and the on-chip oscillator output is selected as the timer A count source. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 83 of 89 7547 Group Notes on Output Compare 1. When the selected source timer of each compare channel is stopped, written data to compare register is loaded to the compare latch simultaneously. 2. Do not write the same data to both of compare latch x0 (x=0, 1, 2, 3) and x1. 3. When setting value of the compare register is larger than timer setting value, compare match signal is not generated. Accordingly, the output waveform is fixed to "L" or "H" level. However, when setting value of another compare register is smaller than timer setting value, this compare match signal is generated. Accordingly, if the corresponding compare latch y (y=00, 01, 10, 11, 20, 21, 30, 31) interrupt source bit is set to "1" (valid), compare match interrupt request occurs. 4. When the compare x trigger enable bit is cleared to "0" (disabled), the match trigger to the waveform output circuit is disabled. Accordingly, the output waveform can be fixed to "L" or "H" level. However, in this case, the compare match signal is generated. Accordingly, if the corresponding compare latch y (y=00, 01, 10, 11, 20, 21, 30, 31) interrupt source bit is set to "1" (valid),compare match interrupt request occurs. Notes on Input Capture 1. If the capture trigger is input while the capture register (low-order and high-order) is in read, captured value is changed between high-order reading and low-order reading. Accordingly, some countermeasure by program is recommended, for example comparing the values that twice of read. 2. Timer A cannot be used for the capture source timer in the following state; * XIN oscillation selected by clock division ratio selection bits (bits 7 and 6 of CPU mode register (address 3B16)) * Timer A count source: On-chip oscillator output. Timer B cannot be used for the capture source timer in the following state; * XIN oscillation selected by clock division ratio selection bits * Timer B count source: Timer A underflow * Timer A count source: On-chip oscillator output. 3. As shown below, when the capture input is performed to both capture latch 00 and 01 at the same time, the value of capture 0 status bit (bit 4 of capture/compare status register (address 2216)) is undefined (same as capture 1). * When "1" is written to capture latch 00 software trigger bit (bit 0 of capture software trigger register (address 1316)) and capture latch 01 software trigger bit (bit 1 of capture software trigger register) at the same time * When external trigger of capture latch 00 and software trigger of capture latch 01 occur at the same time * When external trigger of capture latch 01 and software trigger of capture latch 00 occur at the same time 4. When the capture interrupt is used as the interrupt for return from stop mode, set the capture 0 noise filter clock selection bits (bits 5 and 4 of capture mode register (address 2016)) to "00 (Filter stop)" (same as capture 1). Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 84 of 89 7547 Group Notes on Serial I/Oi (i=1, 2) 1. Clock synchronous serial I/O (1) When the transmit operation is stopped, clear the serial I/Oi enable bit and the transmit enable bit to "0" (serial I/Oi and transmit disabled). 3. Notes common to clock synchronous serial I/O and UART (1) Set the serial I/Oi (i=1, 2) control register again after the transmission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to "0." Clear both the transmit enable bit (TE) and the receive enable bit (RE) to "0" Set the bits 0 to 3 and bit 6 of the serial I/Oi control register Set both the transmit enable bit (TE) and the receive enable bit (RE), or one of them to "1" Can be set with the LDM instruction at the same time Fig. 7 Sequence of setting serial I/Oi control register again (2) The transmit shift completion flag changes from "1" to "0" with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. (3) When data transmission is executed at the state that an external clock input is selected as the synchronous clock, set "1" to the transmit enable bit while the SCLKi is "H" state. Also, write to the transmit buffer register while the SCLKi is "H" state. (4) When the transmit interrupt is used, set as the following sequence. Serial I/Oi transmit interrupt enable bit is set to "0" (disabled). Serial I/Oi transmit enable bit is set to "1". Serial I/Oi transmit interrupt request bit is set to "0" after 1 or more instructions have been executed. Serial I/Oi transmit interrupt enable bit is set to "1" (enabled). Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 85 of 89 7547 Group Notes on Serial I/O1 1. I/O pin function when serial I/O1 is enabled. The pin functions of P12/SCLK1 and P13/SRDY1 are switched to as follows according to the setting values of a serial I/O1 mode selection bit (bit 6 of serial I/O1 control register (address 1A16)) and a serial I/O1 synchronous clock selection bit (bit 1 of serial I/O1 control register). (1) Serial I/O1 mode selection bit "1" : Clock synchronous type serial I/O is selected. * Setup of a serial I/O1 synchronous clock selection bit "0" : P12 pin turns into an output pin of a synchronous clock. "1" : P12 pin turns into an input pin of a synchronous clock. * Setup of a SRDY1 output enable bit (SRDY) "0" : P13 pin can be used as a normal I/O pin. "1" : P13 pin turns into a SRDY1 output pin. (2) Serial I/O1 mode selection bit "0" : Clock asynchronous (UART) type serial I/O is selected. * Setup of a serial I/O1 synchronous clock selection bit "0": P12 pin can be used as a normal I/O pin. "1": P12 pin turns into an input pin of an external clock. * When clock asynchronous (UART) type serial I/O is selected, it functions P13 pin. It can be used as a normal I/O pin. Notes on Serial I/O2 1. I/O pin function when serial I/O2 is enabled The pin functions of P06/SCLK2 and P07/SRDY2 are switched to as follows according to the setting values of a serial I/O2 mode selection bit (bit 6 of serial I/O2 control register (address 3016)) and a serial I/O2 synchronous clock selection bit (bit 2 of serial I/O2 control register). (1) Serial I/O2 mode selection bit "1" : Clock synchronous type serial I/O is selected. * Setup of a serial I/O2 synchronous clock selection bit "0" : P06 pin turns into an output pin of a synchronous clock. "1" : P06 pin turns into an input pin of a synchronous clock. * Setup of a SRDY2 output enable bit (SRDY) "0" : P07 pin can be used as a normal I/O pin. "1" : P07 pin turns into a SRDY2 output pin. (2) Serial I/O2 mode selection bit "0" : Clock asynchronous (UART) type serial I/O is selected. * Setup of a serial I/O2 synchronous clock selection bit "0": P06 pin can be used as a normal I/O pin. "1": P06 pin turns into an input pin of an external clock. * When clock asynchronous (UART) type serial I/O is selected, it functions P07 pin. It can be used as a normal I/O pin. Note on Bus Collision Detection When serial I/O1 is operating at half-duplex communication, set bus collision detection interrupt to be disabled. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 86 of 89 7547 Group Notes on A/D conversion 1. Analog input pin Make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01F to 1F. Further, be sure to verify the operation of application products on the user side. 5. A/D conversion accuracy As for AD translation accuracy, on the following operating conditions, accuracy may become low. (1) Since the analog circuit inside a microcomputer becomes sensitive to noise when VREF voltage is set up lower than Vcc voltage, accuracy may become low rather than the case where VREF voltage and Vcc voltage are set up to the same value.. (2) When VREF voltage is lower than [ 3.0 V ], the accuracy at the low temperature may become extremely low compared with that at room temperature. When the system would be used at low temperature, the use at VREF=3.0 V or more is recommended. Notes on Watchdog Timer 1. The watchdog timer is operating during the wait mode. Write data to the watchdog timer control register to prevent timer underflow. 2. The watchdog timer stops during the stop mode. However, the watchdog timer is running during the oscillation stabilizing time after the STP instruction is released. In order to avoid the underflow of the watchdog timer, the watchdog timer count source selection bit (bit 7 of watchdog timer control register (address 3916)) before executing the STP instruction. 3. The STP instruction function selection bit (bit 6 of watchdog timer control register (address 3916)) can be rewritten only once after releasing reset. After rewriting it is disable to write any data to this bit. Notes on RESET pin 1. Connecting capacitor In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the RESET pin and the Vss pin. And use a 1000 pF or more capacitor for high frequency use. When connecting the capacitor, note the following : * Make the length of the wiring which is connected to a capacitor as short as possible. * Be sure to verify the operation of application products on the user side. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 87 of 89 7547 Group Notes on Clock Generating Circuit 1. Switch of ceramic and RC oscillations After releasing reset, the oscillation mode selection bit (bit 5 of CPU mode register (address 3B16)) is "0" (ceramic oscillation selected). When the RC oscillation is used, after releasing reset, set this bit to "1". 2. Double-speed mode The double-speed mode can be used only when a ceramic oscillation is selected. Do not use it when an RC oscillation is selected. 3. CPU mode register Oscillation mode selection bit (bit 5), processor mode bits (bits 1 and 0) of CPU mode register (address 3B16) are used to select oscillation mode and to control operation modes of the microcomputer. In order to prevent the dead-lock by erroneously writing (ex. program run-away), these bits can be rewritten only once after releasing reset. After rewriting, it is disabled to write any data to the bit. (The emulator MCU "M37542RSS" is excluded.) Also, when the read-modify-write instructions (SEB, CLB, etc.) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. 4. Clock division ratio, XIN oscillation control, on-chip oscillator control The state transition shown in Fig. 74 can be performed by setting the clock division ratio selection bits (bits 7 and 6), XIN oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of CPU mode register. Be careful of notes on use in Fig. 74. 5. On-chip oscillator operation When the MCU operates by the on-chip oscillator for the main clock, connect XIN pin to VCC through a 1 k to 10 k resistor and leave XOUT pin open. The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that this margin of frequencies when designing application products. 6. Ceramic resonator When the ceramic resonator is used for the main clock, connect the ceramic resonator and the external circuit to pins XIN and XOUT at the shortest distance. Externally connect a damping resistor Rd depending on the oscillation frequency. A feedback resistor is built-in. Use the resonator manufacturer's recommended value because constants such as capacitance depend on the resonator. 7. RC oscillation When the RC oscillation is used for the main clock, connect the XIN pin and XOUT pin to the external circuit of resistor R and the capacitor C at the shortest distance. The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. 8. External clock When the external signal clock is used for the main clock, connect the XIN pin to the clock source and leave XOUT pin open. Select "0" (ceramic oscillation) to oscillation mode selection bit. 9. Count source (Timer 1, Timer A, Timer B, Timer X, Serial I/O, Serial I/O2, A/D converter, Watchdog timer) The count sources of these functions are affected by the clock division selection bit of the CPU mode register. The f(XIN) clock is supplied to the watchdog timer when selecting f(XIN) as the CPU clock. The on-chip oscillator output is supplied to these functions when selecting the on-chip oscillator output as the CPU clock. However, the watchdog timer is also affected by the function set ROM. Notes on Oscillation Control 1. Oscillation stop detection circuit (1) When the stop mode is used, set the oscillation stop detection function to "invalid". (2) When the ceramic or RC oscillation is stopped by the XIN oscillation control bit (bit 4 of CPU mode register (address 3B16)), set the oscillation stop detection function to "invalid". 2. Stop mode (1) When the stop mode is used, set the oscillation stop detection function to "invalid". (2) When the stop mode is used, set "0" (STP instruction enabled) to the STP instruction function selection bit of the watchdog timer control register (bit 6 of watchdog timer control register (address 3916)). (3) The oscillation stabilizing time after release of STP instruction can be selected from "set automatically "/"not set automatically" by the oscillation stabilizing time set bit after release of the STP instruction (bit 0 of MISRG (address 3816)). When "0" is set to this bit, "0116" is set to timer 1 and "FF16" is set to prescaler 1 automatically at the execution of the STP instruction. When "1" is set to this bit, set the wait time to timer 1 and prescaler 1 according to the oscillation stabilizing time of the oscillation. Also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. (4) Do not execute the STP instruction during the A/D conversion. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 88 of 89 7547 Group Notes on On-chip Oscillation Division Ratio * When the clock division ratio is switched from f(XIN) to on-chip oscillator by the clock division ratio selection bits (bits 7 and 6 of CPU mode register (address 3B16)), the on-chip oscillator division ratio (bits 1 and 0 of on-chip oscillation division ratio selection register (address 3716)) is "102" (on-chip oscillator middle-speed mode (ROSC/8)). NOTES ON HARDWARE Handling of Power Source Pin In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F to 0.1 F is recommended. Notes on Oscillation Stop Detection Circuit 1. After the reset by the oscillation stop detection, the value of following bits are retained, not initialized. * Ceramic or RC oscillation stop detection function active bit Bit 1 of MISRG (address 3B16) * Oscillation stop detection status bit Bit 3 of MISRG 2. Oscillation stop detection status bit is initialized ("0") by the following operation. * External reset * Write "0" data to the ceramic or RC oscillation stop detection function active bit. 3. The oscillation stop detection circuit is not included in the emulator MCU "M37542RSS". NOTES ON QzROM Notes On QzROM Writing Orders When ordering the QzROM product shipped after writing, submit the mask file (extension: .mask) which is made by the mask file converter MM. Be sure to set the ROM option ("MASK option" written in the mask file converter) setup when making the mask file by using the mask file converter MM. Notes On ROM Code Protect (QzROM product shipped after writing) As for the QzROM product shipped after writing, the ROM code protect is specified according to the ROM option setup data in the mask file which is submitted at ordering. Renesas Technology corp. write the value of the ROM option setup data in the ROM code protect address (address FFDB16) when writing to the QzROM. As a result, in the contents of the ROM code protect address the ordered value may differ from the actual written value. The ROM option setup data in the mask file is "0016" for protect enabled or "FF16" for protect disabled. Therefore, the contents of the ROM code protect address (other than the user ROM area) of the QzROM product shipped after writing is "0016" or "FF16". Note that the mask file which has nothing at the ROM option data or has the data other than "0016" and "FF16" can not be accepted. Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. Product shipped in blank As for the product shipped in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approx.0.1 % may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing environment may cause some writing errors. DATA REQUIRED FOR QzROM WRITING ORDERS The following are necessary when ordering a QzROM product shipped after writing: 1. QzROM Writing Confirmation Form* 2. Mark Specification Form* 3. ROM data...........Mask file * For the QzROM writing confirmation form and the mark specification form, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com/homepage.jsp). Note that we cannot deal with special font marking (customer's trademark etc.) in QzROM microcomputer. Rev.1.21 Nov 15, 2006 REJ03B0156-0121 page 89 of 89 REVISION HISTORY Rev. Date Page 1.00 Oct 14, 2005 1.10 Jun 05, 2006 - - 2,4,6,79 1 2 3 6 19 36 38 53 59 64 71 72 7547 Group Datasheet Description Summary 73 74 75, 76 77 78 80 6 51, 87 56, 88 67 72 74 87 70 1.20 Aug 30, 2006 1.21 Nov 15, 2006 First Edition issued "Preliminary" eliminated. Package revised. PRSP0036GA-A PRSP0036GA-B Power dissipation added. Fig.1: part number added. Power source voltage (at on-chip oscillator) and power dissipation added. Memory expansion plan: "Under development" eliminated. Notes on use (2): $0Bn $0B Notes on Input Capture; 2nd note: some description added. Block diagram of capture channel 0: address of capture pointer revised. Low Voltage Detection Circuit: bit number of the function set ROM data 0 revised. State transition: (4) revised. Wiring for the VPP pin of the QzPROM revised. Electrical characteristics (1) VRAM Min. value is added. Electrical characteristics (2) - Parameter The condition is added. - Limits Typ. and Max. values are changed. A/D Converter characteristics - Absolute accuracy Max. value is revised. Power-on reset circuit characteristics and Low voltage detection circuit added. Timing requirements is added. Switching characteristics is added. Timing chart added. 4.BRK instruction eliminated. Table 3: ROM size revised and note added. Notes on watchdog timer: note 3 revised. Notes on clock generating circuit: note added. 5. Setup for I/O ports: Note eliminated. Electrical characteristics (2) - Low voltage detection circuit self consumption current added. Low voltage detection circuit characteristics. - Unit of VLVD mV V (1) Analog input pin: description revised. All f(XIN): VCC condition added. A-1 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 (c) 2006. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .7.0 |
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